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* Revert "AArch64: Fix frame record chain"Logan Chien2019-12-141-29/+0
* AArch64: Fix frame record chainLogan Chien2019-12-141-0/+29
* [AArch64][test] Fix machine-outliner-size-info.mir after D71168Fangrui Song2019-12-141-0/+1
* [AArch64] add tests for fcvtl2; NFCSanjay Patel2019-12-141-0/+49
* [AArch64] Save FP for leaf functions when disabling frame pointer eliminationFangrui Song2019-12-139-21/+25
* [Legalizer] Making artifact combining order-independentRoman Tereshin2019-12-134-19/+16
* [DAGCombiner] fold shift-trunc-shift to shift-mask-trunc (2nd try)Sanjay Patel2019-12-131-2/+1
* [PGO][PGSO] Enable size optimizations in code gen / target passes for cold code.Hiroshi Yamauchi2019-12-132-0/+261
* [AArch64] Emit PAC/BTI .note.gnu.property flagsMomchil Velikov2019-12-139-0/+185
* Recommit "[AArch64][SVE] Implement intrinsics for non-temporal loads & stores"Kerry McLaughlin2019-12-132-0/+183
* hwasan: add tag_offset DWARF attribute to optimized debug infoEvgenii Stepanov2019-12-121-0/+68
* [AArch64][SVE] Add integer arithmetic with immediate instructions.Danilo Carvalho Grael2019-12-121-0/+471
* Revert "[DAGCombiner] fold shift-trunc-shift to shift-mask-trunc"Sanjay Patel2019-12-121-1/+2
* [DAGCombiner] fold shift-trunc-shift to shift-mask-truncSanjay Patel2019-12-121-2/+1
* [AArch64][PowerPC] add tests for shift sandwich; NFCSanjay Patel2019-12-121-0/+13
* [AArch64][SVE] Add patterns for scalable vselectCameron McInally2019-12-111-0/+85
* [AArch64][x86] add tests for possible infinite loops in DAGCombiner; NFCSanjay Patel2019-12-111-2/+30
* Revert "[SDAG] remove use restriction in isNegatibleForFree() when called fro...Sanjay Patel2019-12-111-18/+0
* Add intrinsics for unary narrowing operationsAndrzej Warzynski2019-12-111-0/+202
* [AArch64] Be more careful to skip debug operands in LdSt Optimizier.Florian Hahn2019-12-111-3/+39
* [SDAG] remove use restriction in isNegatibleForFree() when called from getNeg...Sanjay Patel2019-12-111-0/+18
* [AArch64] Skip debug ops with regsOverlap in AArch64 LD/ST opt.Florian Hahn2019-12-111-0/+49
* Revert "[AArch64][SVE] Implement intrinsics for non-temporal loads & stores"Kerry McLaughlin2019-12-112-183/+0
* [AArch64] Teach Load/Store optimizier to rename store operands for pairing.Florian Hahn2019-12-116-44/+502
* [AArch64][SVE] Add DAG combine rules for gather loads and sext/zextAndrzej Warzynski2019-12-116-86/+405
* Revert "Reland [AArch64][MachineOutliner] Return address signing for outlined...Oliver Stannard2019-12-1111-987/+0
* [AArch64][SVE] Implement intrinsics for non-temporal loads & storesKerry McLaughlin2019-12-112-0/+183
* [AArch64] Fix issues with large arrays on stackKiran Chandramohan2019-12-101-0/+49
* [AArch64][SVE] Add wide compare immediate patternsCullen Rhodes2019-12-101-0/+404
* [AArch64][SVE] Implement SPLAT_VECTOR for i1 vectors.Eli Friedman2019-12-091-0/+40
* [PGO][PGSO] Instrument the code gen / target passes.Hiroshi Yamauchi2019-12-092-1/+14
* [AArch64][GlobalISel] Add support for selection of vector G_SHL with immediates.Amara Emerson2019-12-062-16/+196
* Revert "[PGO][PGSO] Instrument the code gen / target passes."Hiroshi Yamauchi2019-12-062-14/+1
* [PGO][PGSO] Instrument the code gen / target passes.Hiroshi Yamauchi2019-12-062-1/+14
* [MBP] Avoid tail duplication if it can't bring benefitGuozhi Wei2019-12-063-4/+4
* [AArch64] Fix a bug with jump table generationCullen Rhodes2019-12-061-0/+83
* [AArch64][SVE2] Implement while comparison intrinsicsCullen Rhodes2019-12-061-0/+309
* [AArch64][SVE] Implement integer compare intrinsicsCullen Rhodes2019-12-062-0/+1594
* [AArch64] Fix MUL/SUB fusingSanne Wouda2019-12-051-0/+72
* [AArch64][SVE] Integer reduction instructions pattern/intrinsics.Danilo Carvalho Grael2019-12-051-0/+400
* [AArch64][SVE] Implement element count intrinsicsCullen Rhodes2019-12-051-0/+99
* [AArch64][SVE] Add intrinsics and patterns for logical predicate instructionsDanilo Carvalho Grael2019-12-043-12/+601
* Reland [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-12-0511-0/+987
* [GlobalISel] Fix compiler crash lowering G_LOAD in AArch64.Amara Emerson2019-12-041-0/+22
* Revert "Reland [AArch64][MachineOutliner] Return address signing for outlined...Sterling Augustine2019-12-0411-987/+0
* Reland [AArch64][MachineOutliner] Return address signing for outlined functionsDavid Tellenbach2019-12-0411-0/+987
* [SVE][AArch64] Adding patterns for while intrinsics.Mikhail Gudim2019-12-041-0/+309
* [AArch64][SVE] Implement reversal intrinsicsCullen Rhodes2019-12-041-0/+166
* [MacroFusion] Limit the max fused number as 2 to reduce the dependencyQingShan Zhang2019-12-041-6/+3
* [AArch64] Fix over-eager fusing of NEON SIMD MUL/ADDSanne Wouda2019-12-032-31/+43
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