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* [AArch64] Rewrite stack frame handling for win64 vararg functionsMartin Storsjo2017-08-012-4/+111
* Revert "[DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector."Nirav Dave2017-08-012-5/+8
* [DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector.Nirav Dave2017-08-012-8/+5
* [GISel]: Support Widening G_ICMP's destination operand.Aditya Nandakumar2017-07-316-31/+63
* [AArch64] Tie source and destination operands for AESMC/AESIMC. Florian Hahn2017-07-291-83/+47
* [AArch64] Use 8 bytes as preferred function alignment on Cortex-A53.Florian Hahn2017-07-291-1/+1
* GlobalISel: map 128-bit values to an FPR by default.Tim Northover2017-07-282-18/+21
* [AArch64] Fix legality info passed to demanded bits for TBI opt.Ahmed Bougacha2017-07-271-0/+11
* [AArch64] Add a test for float argument passing to win64 vararg functionsMartin Storsjo2017-07-251-0/+26
* [AArch64] Reserve a 16 byte aligned amount of fixed stack for win64 varargsMartin Storsjo2017-07-252-11/+65
* [AArch64] Add test for function alignment for a optsize function (NFC). Florian Hahn2017-07-231-17/+24
* [AArch64] Redundant Copy Elimination - remove more zero copies.Chad Rosier2017-07-231-0/+565
* Recommit: GlobalISel: select G_EXTRACT and G_INSERT instructions on AArch64.Tim Northover2017-07-201-0/+54
* GlobalISel: stop localizer putting constants before EH_LABELsTim Northover2017-07-201-0/+48
* Add an ID field to StackObjectsMatt Arsenault2017-07-202-5/+9
* Revert "GlobalISel: select G_EXTRACT and G_INSERT instructions on AArch64."Diana Picus2017-07-201-54/+0
* [PEI] Add basic opt-remarks supportFrancis Visoiu Mistrih2017-07-191-0/+57
* GlobalISel: fix SUBREG_TO_REG implementation.Tim Northover2017-07-191-2/+2
* GlobalISel: select G_EXTRACT and G_INSERT instructions on AArch64.Tim Northover2017-07-191-0/+54
* [SimplifyCFG] Defer folding unconditional branches to LateSimplifyCFG if it c...Balaram Makam2017-07-191-3/+3
* [COFF, ARM64] Reserve X18 register by defaultMandeep Singh Grang2017-07-181-0/+1
* [DAG] Improve Aliasing of operations to static allocaNirav Dave2017-07-186-33/+30
* [AArch64][Falkor] Avoid HW prefetcher tag collisions (step 2)Geoff Berry2017-07-182-0/+119
* [globalisel][tablegen] Enable the import of rules involving fma.Daniel Sanders2017-07-181-0/+41
* [AArch64] Use 16 bytes as preferred function alignment on Cortex-A73.Florian Hahn2017-07-181-1/+1
* Revert r308025 due to uncovering a crash in SelectionDAG. This is filedChandler Carruth2017-07-186-30/+33
* [AArch64] Extend CallingConv::X86_64_Win64 to AArch64 as wellMartin Storsjo2017-07-171-0/+74
* [llvm] Remove redundant check-prefix=CHECK from tests. NFC.Mandeep Singh Grang2017-07-172-2/+2
* [AArch64] Avoid selecting XZR inline ASM memory operandYi Kong2017-07-141-0/+10
* [AArch64][Falkor] Avoid HW prefetcher tag collisions (step 1)Geoff Berry2017-07-141-0/+106
* Improve Aliasing of operations to static allocaNirav Dave2017-07-146-33/+30
* [AArch64] Implement support for windows style vararg functionsMartin Storsjo2017-07-131-0/+95
* [AArch64] Add preliminary support for ARMv8.1 SUB/AND atomicsMatthew Simpson2017-07-131-0/+161
* GlobalISel: Handle selection of G_IMPLICIT_DEF in AArch64Justin Bogner2017-07-121-0/+30
* [CodeGen] Add dependency printerEvandro Menezes2017-07-124-10/+10
* Enhance synchscope representationKonstantin Zhuravlyov2017-07-112-5/+5
* [globalisel][tablegen] Correct matching of intrinsic ID's.Daniel Sanders2017-07-111-0/+38
* Revert "[DAG] Improve Aliasing of operations to static alloca"Matthias Braun2017-07-106-30/+33
* [DAG] Improve Aliasing of operations to static allocaNirav Dave2017-07-106-33/+30
* [AArch64] Use 16 bytes as preferred function alignment on Cortex-A57.Florian Hahn2017-07-071-1/+1
* [AArch64] Use 16 bytes as preferred function alignment on Cortex-A72.Florian Hahn2017-07-071-1/+1
* [AArch64] Add test case for preferred function alignment (NFC). Florian Hahn2017-07-071-0/+26
* [ORE] Add diagnostics hotness thresholdBrian Gesiak2017-06-301-0/+27
* GlobalISel: add G_IMPLICIT_DEF instruction.Tim Northover2017-06-305-17/+47
* [GISel]: New Opcode G_FLOG/G_FLOG2Aditya Nandakumar2017-06-291-0/+19
* [AArch64] AArch64CondBrTuningPass generates wrong branch instructionsAlexandros Lamprineas2017-06-281-4/+4
* [GISel]: Add G_FEXP, G_FEXP2 opcodesAditya Nandakumar2017-06-271-0/+20
* GlobalISel: verify that a COPY is trivial when created.Tim Northover2017-06-271-1/+1
* [AArch64] Update successor probabilities after ccmp-conversionMatthew Simpson2017-06-272-3/+49
* [globalisel][tablegen] Add support for EXTRACT_SUBREG.Daniel Sanders2017-06-271-2/+2
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