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path: root/llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
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* [AArch64] Improve FP16 instruction selection for vector round and vector conv...Abderrazek Zaafrani2019-03-061-29/+35
* [AArch64] Improve FP16 vector convert from short instructions.Abderrazek Zaafrani2019-02-281-14/+16
* [AArch64] Generate FP16 vector compare instructions.Abderrazek Zaafrani2019-02-281-112/+18
* [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm testsJoel E. Denny2018-07-111-2/+2
* [AArch64][TableGen] Skip tied result operands for InstAliasSander de Smalen2017-11-201-19/+22
* [AArch64] allow v8f16 types when FullFP16 is supportedSjoerd Meijer2017-09-151-147/+336
* Revert r294437 as it broke an asan buildbot.Amara Emerson2017-02-081-19/+19
* [AArch64][TableGen] Skip tied result operands for InstAliasAmara Emerson2017-02-081-19/+19
* Do not lower VSETCC if operand is an f16 vectorPirama Arumuga Nainar2016-01-221-0/+84
* Fix fptosi, fptoui from f16 vectors to i8, i16 vectorsPirama Arumuga Nainar2015-12-101-0/+54
* Define selection for v4f16, v8f16 scalar_to_vectorPirama Arumuga Nainar2015-12-081-0/+9
* [AArch64] Handle vec4, vec8, vec16 *itofp for halfPirama Arumuga Nainar2015-04-231-1/+107
* [opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie2015-02-271-1/+1
* [AArch64] Prefer DUP/MOV ("CPY") to INS for vector_extract.Ahmed Bougacha2015-02-021-4/+4
* Teach the AArch64 backend about v4f16 and v8f16Oliver Stannard2014-08-271-0/+255
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