bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	Change the fast-isel-abort option from bool to int to enable "levels"	Mehdi Amini	2015-02-27	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 230775
*	[FastISel][AArch64] Simplify mul to shift when possible.	Juergen Ributzka	2014-09-17	1	-28/+32
\| \| \| \| \| \|	This is related to rdar://problem/18369687. llvm-svn: 217980
*	[FastISel][AArch64] Use the correct register class to make the MI verifier ↵	Juergen Ributzka	2014-08-21	1	-5/+5
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	happy. This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPRAllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_ method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. llvm-svn: 216225
*	AArch64: correctly fast-isel i8 & i16 multiplies	Tim Northover	2014-07-10	1	-0/+40
	We were asking for a register for type i8 or i16 which caused an assert. rdar://problem/17620015 llvm-svn: 212718