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bcm5719-llvm
meklort-10.0.0
meklort-10.0.1
ortega-7.0.1
Project Ortega BCM5719 LLVM
Raptor Computing Systems
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path:
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llvm
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test
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CodeGen
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AArch64
/
arm64-zero-cycle-zeroing.ll
Commit message (
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Author
Age
Files
Lines
*
AArch64: add missing Apple CPU names and use them by default.
Tim Northover
2020-01-08
1
-0
/
+1
*
[clang][llvm] Obsolete Exynos M1 and M2
Evandro Menezes
2019-10-30
1
-1
/
+0
*
[AArch64] Do 64-bit vector move of 0 and -1 by extracting from the 128-bit move
John Brawn
2018-10-25
1
-4
/
+4
*
[AArch64] Split zero cycle feature more granularly
Evandro Menezes
2018-09-28
1
-34
/
+168
*
[AArch64] Don't materialize 0 with "fmov h0, .." when FullFP16 is not supported
Sjoerd Meijer
2018-02-08
1
-5
/
+8
*
[AArch64] Expand testing of zero cycle zeroing
Evandro Menezes
2018-01-30
1
-34
/
+29
*
AArch64: fix one more place movi.2d could be created.
Tim Northover
2017-12-20
1
-0
/
+9
*
AArch64: work around how Cyclone handles "movi.2d vD, #0".
Tim Northover
2017-12-18
1
-6
/
+6
*
[AArch64] Update the feature set for Qualcomm's Falkor CPU.
Chad Rosier
2017-01-04
1
-0
/
+7
*
[AArch64] Set FMOVS0 and FMOVD0 as isAsCheapAsAMove when needed.
Haicheng Wu
2016-07-12
1
-4
/
+4
*
[Kryo] Enable ZCZeroing feature
Haicheng Wu
2016-07-12
1
-22
/
+30
*
AArch64: Change modeling of zero cycle zeroing.
Matthias Braun
2016-07-06
1
-0
/
+26
*
AArch64: allow MOV (imm) alias to be printed
Tim Northover
2016-06-16
1
-4
/
+4
*
AArch64/ARM64: move ARM64 into AArch64's place
Tim Northover
2014-05-24
1
-0
/
+49