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path: root/llvm/test/CodeGen/AArch64/arm64-st1.ll
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* [clang][llvm] Obsolete Exynos M1 and M2Evandro Menezes2019-10-301-2/+2
* [AArch64] Improve single vector lane unscaled storesEvandro Menezes2018-05-151-53/+74
* [AArch64] Improve single vector lane storesEvandro Menezes2018-05-141-0/+205
* [AArch64] Avoid SIMD interleaved store instruction for Exynos.Abderrazek Zaafrani2017-12-081-0/+107
* [AARCH64] Enable AARCH64 lit tests on windows dev machinesSimon Pilgrim2016-07-191-1/+1
* Add a bunch of CHECK missing colons in tests. NFC.Ahmed Bougacha2015-03-141-24/+25
* [opaque pointer type] Add textual IR support for explicit type parameter to g...David Blaikie2015-02-271-20/+20
* [AArch64] Improve codegen of store lane instructions by avoiding GPR usage.Ahmed Bougacha2015-01-051-4/+104
* [AArch64] Improve codegen of store lane 0 instructions by directly storing th...Ahmed Bougacha2015-01-051-0/+92
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-0/+676
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