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* [X86] Fix MSVC "truncation from 'int' to 'bool'" warning. NFCI.Simon Pilgrim2020-01-131-2/+2
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* ARMLowOverheadLoops: return earlier to avoid printing irrelevant dbg msg. NFCSjoerd Meijer2020-01-131-0/+1
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* This option allows selecting the TLS size in the local exec TLS model,KAWASHIMA Takahiro2020-01-133-26/+117
| | | | | | | | | | | | | | | | | | which is the default TLS model for non-PIC objects. This allows large/ many thread local variables or a compact/fast code in an executable. Specification is same as that of GCC. For example, the code model option precedes the TLS size option. TLS access models other than local-exec are not changed. It means supoort of the large code model is only in the local exec TLS model. Patch By KAWASHIMA Takahiro (kawashima-fj <t-kawashima@fujitsu.com>) Reviewers: dmgreen, mstorsjo, t.p.northover, peter.smith, ostannard Reviewd By: peter.smith Committed by: peter.smith Differential Revision: https://reviews.llvm.org/D71688
* [RISCV] Collect Statistics on Compressed InstructionsSam Elliott2020-01-132-0/+14
| | | | | | | | | | | | | | | | | Summary: It is useful to keep statistics on how many instructions we have compressed, so we can see if future changes are increasing or decreasing this number. Reviewers: asb, luismarques Reviewed By: asb, luismarques Subscribers: xbolva00, sameer.abuasal, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67495
* [SCEV] Follow up of D71563: addressing post commit comment. NFC.Sjoerd Meijer2020-01-131-11/+6
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* [DWARF5][DebugInfo]: Added support for DebugInfo generation for auto return ↵Awanish Pandey2020-01-131-0/+8
| | | | | | | | | | | | | | | | | | type for C++ member functions. Summary: This patch will provide support for auto return type for the C++ member functions. Before this return type of the member function is deduced and stored in the DIE. This patch includes llvm side implementation of this feature. Patch by: Awanish Pandey <Awanish.Pandey@amd.com> Reviewers: dblaikie, aprantl, shafik, alok, SouraVX, jini.susan.george Reviewed by: dblaikie Differential Revision: https://reviews.llvm.org/D70524
* [X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes.Craig Topper2020-01-121-2/+2
| | | | | At least one of these is used without a Glue. This doesn't seem to change the X86GenDAGISel.inc output so maybe it doesn't matter?
* AMDGPU/GlobalISel: Don't use XEXEC class for SGPRsMatt Arsenault2020-01-121-1/+1
| | | | | We don't use the xexec register classes for arbitrary values anymore. Avoids a test variance beween GlobalISel and SelectionDAG>
* AMDGPU/GlobalISel: Copy type when inserting readfirstlaneMatt Arsenault2020-01-121-0/+2
| | | | | getDefIgnoringCopies will fail to find any def if no type is set if we try to use it on the use's operand, so propagate the type.
* [SCEV] accurate range for addrecexpr with nuw flagZheng Chen2020-01-121-5/+6
| | | | | | | | | If addrecexpr has nuw flag, the value should never be less than its start value and start value does not required to be SCEVConstant. Reviewed By: nikic, sanjoy Differential Revision: https://reviews.llvm.org/D71690
* [RISCV] Check register class for AMO memory operandsJames Clarke2020-01-132-1/+6
| | | | | | | | | | | | | | | | | | | Summary: AMO memory operands use a custom parser in order to accept both (reg) and 0(reg). However, the validation predicate used for these operands was only checking that they were registers, and not the register class, so non-GPRs (such as FPRs) were also accepted. Thus, fix this by making the predicate check that they are GPRs. Reviewers: asb, lenary Reviewed By: asb, lenary Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72471
* [MC][ELF] Emit a relocation if target is defined in the same section and is ↵Fangrui Song2020-01-121-21/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | non-local For a target symbol defined in the same section, currently we don't emit a relocation if VariantKind is VK_None (with few exceptions like RISC-V relaxation), while GNU as emits one. This causes program behavior differences with and without -ffunction-sections, and can break intended symbol interposition in a -shared link. ``` .globl foo foo: call foo # no relocation. On other targets, may be written as b foo, etc call bar # a relocation if bar is in another section (e.g. -ffunction-sections) call foo@plt # a relocation ``` Unify these cases by always emitting a relocation. If we ever want to optimize `call foo` in -shared links, we should emit a STB_LOCAL alias and call via the alias. ARM/thumb2-beq-fixup.s: we now emit a relocation to global_thumb_fn as GNU as does. X86/Inputs/align-branch-64-2.s: we now emit R_X86_64_PLT32 to foo as GNU does. ELF/relax.s: rewrite the test as target-in-same-section.s . We omitted relocations to `global` and now emit R_X86_64_PLT32. Note, GNU as does not emit a relocation for `jmp global` (maybe its own bug). Our new behavior is compatible except `jmp global`. Reviewed By: peter.smith Differential Revision: https://reviews.llvm.org/D72197
* __patchable_function_entries: don't use linkage field 'unique' with ↵Fangrui Song2020-01-121-18/+21
| | | | | | | | | | | | -no-integrated-as .section name, "flags"G, @type, GroupName[, linkage] As of binutils 2.33, linkage cannot be 'unique'. For integrated assembler, we use both 'o' flag and 'unique' linkage to support --gc-sections and COMDAT with lld. https://sourceware.org/ml/binutils/2019-11/msg00266.html
* [NFC] Fix compilation of CrashRecoveryContext.cpp on mingwMarkus Böck2020-01-121-1/+2
| | | | | | Patch by Markus Böck. Differential Revision: https://reviews.llvm.org/D72564
* [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwinFangrui Song2020-01-124-201/+1
| | | | | | | | Darwin support has been removed. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D72063
* [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower binary v4f64 shuffles.Simon Pilgrim2020-01-121-0/+12
| | | | | | Only perform this if we are shuffling lower and upper lane elements across the lanes (otherwise splitting to lower xmm shuffles would be better). This is a regression if we shuffle build_vectors due to getVectorShuffle canonicalizing 'blend of splat' build vectors, for now I've set this not to shuffle build_vector nodes at all to avoid this.
* [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the demanded ↵Simon Pilgrim2020-01-121-2/+1
| | | | | | elements of the lane mask. Fixes an cyclic dependency issue with an upcoming patch where getVectorShuffle canonicalizes masks with splat build vector sources.
* [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into ↵Fangrui Song2020-01-124-1868/+1569
| | | | X86Disassembler.cpp and refactor
* [X86][Disassembler] SimplifyFangrui Song2020-01-123-45/+7
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* [NFC] Refactor memory ops cluster methodQiu Chaofan2020-01-121-14/+7
| | | | | | | | | | | Current implementation of BaseMemOpsClusterMutation is a little bit obscure. This patch directly uses a map from store chain ID to set of memory instrs to make it simpler, so that future improvements are easier to read, update and review. Reviewed By: evandro Differential Revision: https://reviews.llvm.org/D72070
* [X86] Don't call LowerSETCC from LowerSELECT for ↵Craig Topper2020-01-111-3/+1
| | | | | | | | | | | STRICT_FSETCC/STRICT_FSETCCS nodes. This causes the STRICT_FSETCC/STRICT_FSETCCS nodes to lowered early while lowering SELECT, but the output chain doesn't get connected. Then we visit the node again when it is its turn because we haven't replaced the use of the chain result. In the case of the fp128 libcall lowering, after D72341 this will cause the libcall to be emitted twice.
* [SCEV] more accurate range for addrecexpr with nsw flag.Zheng Chen2020-01-111-9/+17
| | | | | | Reviewed By: nikic Differential Revision: https://reviews.llvm.org/D72436
* [LegalizeVectorOps] Parallelize the lo/hi part of STRICT_UINT_TO_FLOAT ↵Craig Topper2020-01-111-3/+6
| | | | | | | legalization. The lo and hi computation are independent. Give them the same input chain and TokenFactor the results together.
* [TargetLowering][X86] Connect the chain from STRICT_FSETCC in ↵Craig Topper2020-01-112-5/+9
| | | | TargetLowering::expandFP_TO_UINT and X86TargetLowering::FP_TO_INTHelper.
* [LegalizeVectorOps] Expand vector MERGE_VALUES immediately.Craig Topper2020-01-111-0/+11
| | | | | | Custom legalization can produce MERGE_VALUES to return multiple results. We can expand them immediately instead of leaving them around for DAG combine to clean up.
* [X86][Disassembler] Optimize argument passing and immediate readingFangrui Song2020-01-113-74/+41
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* [Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()Fangrui Song2020-01-1123-75/+38
| | | | | | | | | | The argument is llvm::null() everywhere except llvm::errs() in llvm-objdump in -DLLVM_ENABLE_ASSERTIONS=On builds. It is used by no target but X86 in -DLLVM_ENABLE_ASSERTIONS=On builds. If we ever have the needs to add verbose log to disassemblers, we can record log with a member function, instead of passing it around as an argument.
* [ORC] Fix argv handling in runAsMain / lli.Lang Hames2020-01-111-1/+1
| | | | | | | | This fixes an off-by-one error in the argc value computed by runAsMain, and switches lli back to using the input bitcode (rather than the string "lli") as the effective program name. Thanks to Stefan Graenitz for spotting the bug.
* [Support] Optionally call signal handlers when a function wrapped by the the ↵Alexandre Ganea2020-01-113-53/+85
| | | | | | | | | CrashRecoveryContext fails This patch allows for handling a failure inside a CrashRecoveryContext in the same way as the global exception/signal handler. A failure will have the same side-effect, such as cleanup of temporarty file, printing callstack, calling relevant signal handlers, and finally returning an exception code. This is an optional feature, disabled by default. This is a support patch for D69825. Differential Revision: https://reviews.llvm.org/D70568
* [X86][Disassembler] Replace custom logger with LLVM_DEBUGFangrui Song2020-01-113-56/+14
| | | | | | | llvm-objdump -d on clang is decreased from 7.8s to 7.4s. The improvement is likely due to the elimination of logger setup and dbgprintf(), which has a large overhead.
* [LegalizeVectorOps] Remove some of the simpler Expand methods. Pass Results ↵Craig Topper2020-01-111-125/+77
| | | | | | | | | | | vector to a couple. NFCI Some of the simplest handlers just call TLI and if that fails, they fall back to unrolling. For those just inline the TLI call and share the unrolling call with the default case of Expand. For ExpandFSUB and ExpandBITREVERSE so that its obvious they don't return results sometimes and want to defer to LegalizeDAG.
* [LegalizeVectorOps] Only pass SDNode* instead SDValue to all of the Expand* ↵Craig Topper2020-01-111-251/+251
| | | | | | | and Promote* methods. All the Expand* and Promote* function assume they are being called with result 0 anyway. Just hardcode result 0 into them.
* [X86][Disassembler] Simplify and optimize reader functionsFangrui Song2020-01-113-180/+101
| | | | llvm-objdump -d on clang is decreased from 8.2s to 7.8s.
* [X86] Turn FP_ROUND/STRICT_FP_ROUND into X86ISD::VFPROUND/STRICT_VFPROUND ↵Craig Topper2020-01-113-67/+4
| | | | during PreprocessISelDAG to remove some duplicate isel patterns.
* [ExecutionEngine] Re-enable FastISel for non-iOS arm targets.Lang Hames2020-01-111-7/+0
| | | | | | Patch by Nicolas Capens. Thanks Nicolas! https://reviews.llvm.org/D65015
* [X86] Adjust nop emission by compiler to consider target decode limitationsPhilip Reames2020-01-111-0/+17
| | | | | | The primary motivation of this change is to bring the code more closely in sync behavior wise with the assembler's version of nop emission. I'd like to eventually factor them into one, but that's hard to do when one has features the other doesn't. The longest encodeable nop on x86 is 15 bytes, but many processors - for instance all intel chips - can't decode the 15 byte form efficiently. On those processors, it's better to use either a 10 byte or 11 byte sequence depending.
* [X86AsmBackend] Move static function before sole use [NFC]Philip Reames2020-01-111-34/+34
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* [X86AsmBackend] Be consistent about placing definitions out of line [NFC]Philip Reames2020-01-111-49/+57
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* Fix uninitialized value clang static analyzer warning. NFC.Simon Pilgrim2020-01-111-1/+1
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* moveOperands - assert Src/Dst MachineOperands are non-null.Simon Pilgrim2020-01-111-1/+1
| | | | Fixes static-analyzer warnings.
* [X86] Fix outdated commentSimon Pilgrim2020-01-111-2/+1
| | | | The generic saturated math opcodes are no longer widened inside X86TargetLowering
* [X86][AVX] Add lowerShuffleAsLanePermuteAndSHUFP loweringSimon Pilgrim2020-01-111-0/+40
| | | | | | | | Add initial support for lowering v4f64 shuffles to SHUFPD(VPERM2F128(V1, V2), VPERM2F128(V1, V2)), eventually this could be used for v8f32 (and maybe v8f64/v16f32) but I'm being conservative for the initial implementation as only v4f64 can always succeed. This currently is only called from lowerShuffleAsLanePermuteAndShuffle so only gets used for unary shuffles, and we limit this to cases where we use upper elements as otherwise concating 2 xmm shuffles is probably the better case. Helps with poor shuffles mentioned in D66004.
* DSE: fix bug where we would only check libcalls for name rather than whole declNuno Lopes2020-01-111-9/+12
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* [InstCombine] Preserve nuw on sub of geps (PR44419)Nikita Popov2020-01-112-4/+16
| | | | | | | | | Fix https://bugs.llvm.org/show_bug.cgi?id=44419 by preserving the nuw on sub of geps. We only do this if the offset has a multiplication as the final operation, as we can't be sure the operations is nuw in the other cases without more thorough analysis. Differential Revision: https://reviews.llvm.org/D72048
* [X86] Remove dead code from X86DAGToDAGISel::Select that is no longer needed ↵Craig Topper2020-01-111-28/+0
| | | | now that we don't mutate strict fp nodes. NFC
* [X86] Simplify code by removing an unreachable condition. NFCICraig Topper2020-01-101-12/+2
| | | | | | For X87<->SSE conversions, the SSE type is always smaller than the X87 type. So we can always use the smallest type for the memory type.
* [X86] Preserve fpexcept property when turning strict_fp_extend and ↵Craig Topper2020-01-102-4/+37
| | | | | | | | | | | strict_fp_round into stack operations. We use the stack for X87 fp_round and for moving from SSE f32/f64 to X87 f64/f80. Or from X87 f64/f80 to SSE f32/f64. Note for the SSE<->X87 conversions the conversion always happens in the X87 domain. The load/store ops in the X87 instructions are able to signal exceptions.
* [X86][Disassembler] Simplify readPrefixesFangrui Song2020-01-101-43/+25
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* [X86] Use ReplaceAllUsesWith instead of ReplaceAllUsesOfValueWith to ↵Craig Topper2020-01-101-12/+2
| | | | simplify some code. NFCI
* [AMDGPU] Remove unnecessary v_mov from a register to itself in WQM lowering.Michael Bedy2020-01-101-5/+22
| | | | | | | | | | | | | | | | | | | Summary: - SI Whole Quad Mode phase is replacing WQM pseudo instructions with v_mov instructions. While this is necessary for the special handling of moving results out of WWM live ranges, it is not necessary for WQM live ranges. The result is a v_mov from a register to itself after every WQM operation. This change uses a COPY psuedo in these cases, which allows the register allocator to coalesce the moves away. Reviewers: tpr, dstuttard, foad, nhaehnle Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D71386
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