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authorSam Elliott <selliott@lowrisc.org>2020-01-13 10:03:33 +0000
committerSam Elliott <selliott@lowrisc.org>2020-01-13 10:04:05 +0000
commitc9babcbda77e69698825cfb9ce771352be93acee (patch)
tree13bcff9f9a005e03b48ff6806a3e01238884ca0a /llvm/lib
parentddf044290ede7d7fd47f4f673e3e628f551a8aac (diff)
downloadbcm5719-llvm-c9babcbda77e69698825cfb9ce771352be93acee.tar.gz
bcm5719-llvm-c9babcbda77e69698825cfb9ce771352be93acee.zip
[RISCV] Collect Statistics on Compressed Instructions
Summary: It is useful to keep statistics on how many instructions we have compressed, so we can see if future changes are increasing or decreasing this number. Reviewers: asb, luismarques Reviewed By: asb, luismarques Subscribers: xbolva00, sameer.abuasal, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67495
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp8
-rw-r--r--llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp6
2 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index fe0455fb222..2a0406de372 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -15,6 +15,7 @@
#include "Utils/RISCVMatInt.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/CodeGen/Register.h"
#include "llvm/MC/MCAssembler.h"
@@ -37,10 +38,15 @@
using namespace llvm;
+#define DEBUG_TYPE "riscv-asm-parser"
+
// Include the auto-generated portion of the compress emitter.
#define GEN_COMPRESS_INSTR
#include "RISCVGenCompressInstEmitter.inc"
+STATISTIC(RISCVNumInstrsCompressed,
+ "Number of RISC-V Compressed instructions emitted");
+
namespace {
struct RISCVOperand;
@@ -1615,6 +1621,8 @@ bool RISCVAsmParser::parseDirectiveOption() {
void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
MCInst CInst;
bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
+ if (Res)
+ ++RISCVNumInstrsCompressed;
S.EmitInstruction((Res ? CInst : Inst), getSTI());
}
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 57631dcb511..7247adf4884 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -16,6 +16,7 @@
#include "MCTargetDesc/RISCVMCExpr.h"
#include "RISCVTargetMachine.h"
#include "TargetInfo/RISCVTargetInfo.h"
+#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -31,6 +32,9 @@ using namespace llvm;
#define DEBUG_TYPE "asm-printer"
+STATISTIC(RISCVNumInstrsCompressed,
+ "Number of RISC-V Compressed instructions emitted");
+
namespace {
class RISCVAsmPrinter : public AsmPrinter {
public:
@@ -64,6 +68,8 @@ void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
MCInst CInst;
bool Res = compressInst(CInst, Inst, *TM.getMCSubtargetInfo(),
OutStreamer->getContext());
+ if (Res)
+ ++RISCVNumInstrsCompressed;
AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
}
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