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* Remove a nested anonymous namespace.Rafael Espindola2014-11-251-2/+0
| | | | llvm-svn: 222728
* Fix overly aggressive type merging.Rafael Espindola2014-11-251-8/+19
| | | | | | | If we find out that two types are *not* isomorphic, we learn nothing about opaque sub types in both the source and destination. llvm-svn: 222727
* Link the type of aliases.Rafael Espindola2014-11-251-2/+5
| | | | | | They are not more or less "well typed" than GlobalVariables. llvm-svn: 222725
* Don't repeat name in comment or duplicate comment. NFC.Rafael Espindola2014-11-251-4/+2
| | | | llvm-svn: 222724
* Use range loops. NFC.Rafael Espindola2014-11-251-12/+10
| | | | llvm-svn: 222723
* [FastISel][AArch64] Fix and extend the tbz/tbnz pattern matching.Juergen Ributzka2014-11-251-19/+20
| | | | | | | | | | The pattern matching failed to recognize all instances of "-1", because when comparing against "-1" we didn't use an APInt of the same bitwidth. This commit fixes this and also adds inverse versions of the conditon to catch more cases. llvm-svn: 222722
* InstSimplify: Handle some simple tautological comparisonsDavid Majnemer2014-11-251-0/+34
| | | | | | | | This handles cases where we are comparing a masked value against itself. The analysis could be further improved by making it recursive but such expense is not currently justified. llvm-svn: 222716
* Revert "unique_ptrify LLVMContextImpl::CAZConstants"David Blaikie2014-11-253-9/+6
| | | | | | | | Missed the complexities of how these elements are destroyed. This reverts commit r222714. llvm-svn: 222715
* unique_ptrify LLVMContextImpl::CAZConstantsDavid Blaikie2014-11-253-6/+9
| | | | llvm-svn: 222714
* [PowerPC] Add the 'attn' instructionHal Finkel2014-11-252-0/+8
| | | | | | | | The attn instruction is not part of the Power ISA, but is documented in the A2 user manual, and is accepted by the GNU assembler for the A2 and the POWER4+. Reported as part of PR21650. llvm-svn: 222712
* [PowerPC] Implement combineRepeatedFPDivisorsHal Finkel2014-11-242-0/+23
| | | | | | | | This does not matter on newer cores (where we can use reciprocal estimates in fast-math mode anyway), but for older cores this allows us to generate better fast-math code where we have multiple FDIVs with a common divisor. llvm-svn: 222710
* Factor check for the assume intrinsic out of checks in ↵Philip Reames2014-11-241-42/+39
| | | | | | | | | | | | | | computeKnownBitsFromAssume We were matching against the assume intrinsic in every check. Since we know that it must be an assume, this is just wasted work. Somewhat surprisingly, matching an intrinsic id is actually relatively expensive. It devolves to a string construction and comparison in Function::isIntrinsic. I originally spotted this because it showed up in a performance profile of my compiler. I've since discovered a separate issue which seems to be the actual root cause, but this is minor perf goodness regardless. I'm likely to follow up with another change to factor out the comparison matching. There's no need to match the compare instruction in every single one of the tests. Differential Revision: http://reviews.llvm.org/D6312 llvm-svn: 222709
* Incorporate review comments from r221742Philip Reames2014-11-241-2/+11
| | | | | | This change implements the comment and style changes Sean requested during post commit review with r221742. Sorry for the delay. llvm-svn: 222707
* Bug 21610: Canonicalize min/max fcmp selects to use ordered comparisonsMatt Arsenault2014-11-241-1/+30
| | | | llvm-svn: 222705
* Remove the unused FindUsedTypes pass.Rafael Espindola2014-11-243-101/+0
| | | | | | It was dead since r134829. llvm-svn: 222684
* Add and use Type::subtypes. NFC.Rafael Espindola2014-11-242-6/+4
| | | | llvm-svn: 222682
* [AArch64] Fix clobber computation in A57LoadBalancing pass.Chad Rosier2014-11-241-1/+7
| | | | | | | Extremely difficult to reproduce, so no test case included. PR21637 llvm-svn: 222677
* Removing unused variable.Colin LeMahieu2014-11-241-1/+0
| | | | llvm-svn: 222676
* [asan/coverage] change the way asan coverage instrumentation is done: ↵Kostya Serebryany2014-11-241-10/+7
| | | | | | instead of setting the guard to 1 in the generated code, pass the pointer to guard to __sanitizer_cov and set it there. No user-visible functionality change expected llvm-svn: 222675
* [PowerPC] Fix PR 21652 - copy st_other bits on symbol assignmentUlrich Weigand2014-11-241-0/+17
| | | | | | | | | | | When processing an assignment in the integrated assembler that sets a symbol to the value of another symbol, we need to copy the st_other bits that encode the local entry point offset. Modeled after MipsTargetELFStreamer::emitAssignment handling of the ELF::STO_MIPS_MICROMIPS flag. llvm-svn: 222672
* More long path name support on Windows, this time in program execution.Paul Robinson2014-11-243-9/+24
| | | | | | | Allows long paths for the executable and redirected stdin/stdout/stderr. Addresses PR21563. llvm-svn: 222671
* [Hexagon] Adding asrh instruction, removing unused multiclasses.Colin LeMahieu2014-11-242-40/+7
| | | | llvm-svn: 222670
* [Hexagon] Adding aslh instruction.Colin LeMahieu2014-11-242-5/+7
| | | | llvm-svn: 222668
* [Hexagon] Adding zxth instruction.Colin LeMahieu2014-11-242-5/+7
| | | | llvm-svn: 222662
* [Hexagon] Adding zxtb instruction.Colin LeMahieu2014-11-242-5/+43
| | | | llvm-svn: 222660
* InstCombine: Don't create an unused instructionDavid Majnemer2014-11-241-2/+1
| | | | | | | | | | We would create an instruction but not inserting it. Not inserting the unused instruction would lead us to verification failure. This fixes PR21653. llvm-svn: 222659
* [mips][microMIPS] Fix JRADDIUSP instructionJozef Kolek2014-11-241-1/+0
| | | | | | | | | Fix JRADDIUSP instruction, remove delay slot flag because this instruction doesn't have delay slot. Differential Revision: http://reviews.llvm.org/D6365 llvm-svn: 222658
* [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructionsJozef Kolek2014-11-245-0/+164
| | | | | | Differential Revision: http://reviews.llvm.org/D5122 llvm-svn: 222653
* [mips][microMIPS] Implement 16-bit instructions registers including ZERO ↵Jozef Kolek2014-11-243-0/+41
| | | | | | | | | | instead of S0 Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17. Differential Revision: http://reviews.llvm.org/D5780 llvm-svn: 222652
* Removing a variable that is initialized but never read. The original author ↵Aaron Ballman2014-11-241-6/+2
| | | | | | has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime. llvm-svn: 222649
* [mips][microMIPS] Implement disassembler support for 16-bit instructionsJozef Kolek2014-11-242-14/+57
| | | | | | | | | | | With the help of new method readInstruction16() two bytes are read and decodeInstruction() is called with DecoderTableMicroMips16, if this fails four bytes are read and decodeInstruction() is called with DecoderTableMicroMips32. Differential Revision: http://reviews.llvm.org/D6149 llvm-svn: 222648
* [X86] Improved target specific combine on VSELECT dag nodes.Andrea Di Biagio2014-11-241-89/+8
| | | | | | | | | | | This patch teaches function 'transformVSELECTtoBlendVECTOR_SHUFFLE' how to convert VSELECT dag nodes to shuffles on targets that do not have SSE4.1. On pre-SSE4.1 targets, we can still perform blend operations using movss/movsd. Also, removed a target specific combine that performed a premature lowering of VSELECT nodes to target specific MOVSS/MOVSD nodes. llvm-svn: 222647
* InstCombine: Don't assume DataLayout is always availableDavid Majnemer2014-11-241-1/+2
| | | | | | | | | We tried to get the result of DataLayout::getLargestLegalIntTypeSize but we didn't have a DataLayout. This resulted in opt crashing. This fixes PR21651. llvm-svn: 222645
* Converted back to Unix format (after my last commit 222632)Elena Demikhovsky2014-11-231-3241/+3241
| | | | llvm-svn: 222636
* [X86] Fixes bug in build_vector v4x32 loweringMichael Kuperstein2014-11-231-3/+6
| | | | | | | | | | | | | r222375 made some improvements to build_vector lowering of v4x32 and v4xf32 into an insertps, but it missed a case where: 1. A single extracted element is used twice. 2. The lower of the two non-zero indexes should be preserved, and the higher should be used for the dest mask. This caused a crash, since the source value for the insertps ends-up uninitialized. Differential Revision: http://reviews.llvm.org/D6377 llvm-svn: 222635
* Add missing override keywords.Craig Topper2014-11-231-2/+2
| | | | llvm-svn: 222634
* Masked Vector Load and Store Intrinsics.Elena Demikhovsky2014-11-2317-3148/+3872
| | | | | | | | | | | | | | Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores. Added SDNodes for masked operations and lowering patterns for X86 code generator. Examples: <16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask) declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask) Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch. http://reviews.llvm.org/D6191 llvm-svn: 222632
* R600: Fix extloads of i1 on R600/EvergreenMatt Arsenault2014-11-231-0/+5
| | | | llvm-svn: 222631
* R600: Fix assert on copy of an i1 on pre-SIMatt Arsenault2014-11-231-1/+2
| | | | | | | i1 is not a legal type on Evergreen, so this combine proceeded and tried to produce a bitcast between i1 and i8. llvm-svn: 222630
* InstCombine: Propagate exact for (sdiv X, Pow2) -> (udiv X, Pow2)David Majnemer2014-11-221-2/+4
| | | | llvm-svn: 222625
* InstCombine: Propagate exact for (sdiv X, Y) -> (udiv X, Y)David Majnemer2014-11-221-1/+3
| | | | llvm-svn: 222624
* InstCombine: Propagate exact for (sdiv -X, C) -> (sdiv X, -C)David Majnemer2014-11-221-4/+6
| | | | llvm-svn: 222623
* Tidied up target triple OS detection. NFCSimon Pilgrim2014-11-225-14/+9
| | | | | | Use Triple::isOS*() helper functions where possible. llvm-svn: 222622
* InstCombine: Propagate exact in (udiv (lshr X,C1),C2) -> (udiv x,C1<<C2)David Majnemer2014-11-221-2/+7
| | | | llvm-svn: 222620
* [x86] Teach the vector shuffle yet another step of canonicalization.Chandler Carruth2014-11-221-2/+13
| | | | | | | | No functionality changed yet, but this will prevent subsequent patches from having to handle permutations of various interleaved shuffle patterns. llvm-svn: 222614
* InstCombine: Propagate NSW/NUW for X*(1<<Y) -> X<<YDavid Majnemer2014-11-221-4/+17
| | | | llvm-svn: 222613
* InstCombine: Propagate NSW for -X * -Y -> X * YDavid Majnemer2014-11-221-3/+10
| | | | llvm-svn: 222612
* InstSimplify: Simplify (sub 0, X) -> X if it's NUWDavid Majnemer2014-11-221-11/+3
| | | | | | This is a generalization of the X - (0 - Y) -> X transform. llvm-svn: 222611
* InstCombine: Silence a parenthesis warningDavid Majnemer2014-11-221-1/+1
| | | | llvm-svn: 222609
* InstCombine: Preserve nsw when folding X*(2^C) -> X << CDavid Majnemer2014-11-221-0/+2
| | | | llvm-svn: 222606
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