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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-11-24 17:44:19 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-11-24 17:44:19 +0000 |
| commit | 3b3197ef95f49329e32635c9f0cbc739d44949d9 (patch) | |
| tree | c9a9c945b7267f54c93e0a9acb87b850cacbda31 /llvm/lib | |
| parent | 6265102c17147ca359571b5fa0077a309520f1f0 (diff) | |
| download | bcm5719-llvm-3b3197ef95f49329e32635c9f0cbc739d44949d9.tar.gz bcm5719-llvm-3b3197ef95f49329e32635c9f0cbc739d44949d9.zip | |
[Hexagon] Adding aslh instruction.
llvm-svn: 222668
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 4 |
2 files changed, 7 insertions, 5 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index a243e14cc0b..8f81beba499 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -713,7 +713,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { case Hexagon::ADD_ri: return isInt<8>(MI->getOperand(2).getImm()); - case Hexagon::ASLH: + case Hexagon::A2_aslh: case Hexagon::ASRH: case Hexagon::A2_sxtb: case Hexagon::A2_sxth: @@ -1303,6 +1303,10 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { case Hexagon::A2_pandfnew: case Hexagon::A2_pandt: case Hexagon::A2_pandtnew: + case Hexagon::A4_paslhf: + case Hexagon::A4_paslhfnew: + case Hexagon::A4_paslht: + case Hexagon::A4_paslhtnew: case Hexagon::A2_porf: case Hexagon::A2_porfnew: case Hexagon::A2_port: @@ -1336,8 +1340,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { case Hexagon::COMBINE_rr_cPt: case Hexagon::COMBINE_rr_cNotPt: return true; - case Hexagon::ASLH_cPt_V4: - case Hexagon::ASLH_cNotPt_V4: case Hexagon::ASRH_cPt_V4: case Hexagon::ASRH_cNotPt_V4: return QRI.Subtarget.hasV4TOps(); diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 4ff068cc290..e91d71d82a7 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -265,6 +265,7 @@ multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> { } } +defm aslh : ALU32_2op_base<"aslh", 0b000>, PredNewRel; defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel; defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel; defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel; @@ -634,11 +635,10 @@ multiclass ALU32_2op_base2<string mnemonic> { } } -defm ASLH : ALU32_2op_base2<"aslh">, PredNewRel; defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel; def : Pat <(shl (i32 IntRegs:$src1), (i32 16)), - (ASLH IntRegs:$src1)>; + (A2_aslh IntRegs:$src1)>; def : Pat <(sra (i32 IntRegs:$src1), (i32 16)), (ASRH IntRegs:$src1)>; |
