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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-11-24 17:11:34 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-11-24 17:11:34 +0000 |
| commit | 098256c5e6c044055e3c90bbc6518d0672d5115a (patch) | |
| tree | d9b048ba40cd9650b1d7209257a83c4319c36d2c /llvm/lib | |
| parent | 06bc0caa1f82696f7dbb5c772f5bf0b885f51ed8 (diff) | |
| download | bcm5719-llvm-098256c5e6c044055e3c90bbc6518d0672d5115a.tar.gz bcm5719-llvm-098256c5e6c044055e3c90bbc6518d0672d5115a.zip | |
[Hexagon] Adding zxth instruction.
llvm-svn: 222662
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 4 |
2 files changed, 7 insertions, 5 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 628f4fe6578..a243e14cc0b 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -718,7 +718,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { case Hexagon::A2_sxtb: case Hexagon::A2_sxth: case Hexagon::A2_zxtb: - case Hexagon::ZXTH: + case Hexagon::A2_zxth: return Subtarget.hasV4TOps(); } @@ -1327,6 +1327,10 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { case Hexagon::A4_pzxtbfnew: case Hexagon::A4_pzxtbt: case Hexagon::A4_pzxtbtnew: + case Hexagon::A4_pzxthf: + case Hexagon::A4_pzxthfnew: + case Hexagon::A4_pzxtht: + case Hexagon::A4_pzxthtnew: case Hexagon::ADD_ri_cPt: case Hexagon::ADD_ri_cNotPt: case Hexagon::COMBINE_rr_cPt: @@ -1336,8 +1340,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { case Hexagon::ASLH_cNotPt_V4: case Hexagon::ASRH_cPt_V4: case Hexagon::ASRH_cNotPt_V4: - case Hexagon::ZXTH_cPt_V4: - case Hexagon::ZXTH_cNotPt_V4: return QRI.Subtarget.hasV4TOps(); } } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 05f4cbe1423..4ff068cc290 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -267,6 +267,7 @@ multiclass ALU32_2op_base<string mnemonic, bits<3> minOp> { defm sxtb : ALU32_2op_base<"sxtb", 0b101>, PredNewRel; defm sxth : ALU32_2op_base<"sxth", 0b111>, PredNewRel; +defm zxth : ALU32_2op_base<"zxth", 0b110>, PredNewRel; // Rd=zxtb(Rs): assembler mapped to Rd=and(Rs,#255). // Compiler would want to generate 'zxtb' instead of 'and' becuase 'zxtb' has @@ -635,7 +636,6 @@ multiclass ALU32_2op_base2<string mnemonic> { defm ASLH : ALU32_2op_base2<"aslh">, PredNewRel; defm ASRH : ALU32_2op_base2<"asrh">, PredNewRel; -defm ZXTH : ALU32_2op_base2<"zxth">, PredNewRel; def : Pat <(shl (i32 IntRegs:$src1), (i32 16)), (ASLH IntRegs:$src1)>; @@ -2320,7 +2320,7 @@ def : Pat<(atomic_store_64 (add (i32 IntRegs:$src2), s11_3ImmPred:$offset), // Map from r0 = and(r1, 65535) to r0 = zxth(r1) def : Pat <(and (i32 IntRegs:$src1), 65535), - (ZXTH (i32 IntRegs:$src1))>; + (A2_zxth (i32 IntRegs:$src1))>; // Map from r0 = and(r1, 255) to r0 = zxtb(r1). def : Pat <(and (i32 IntRegs:$src1), 255), |
