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* [AVX-512] Add scalar vfmsub/vfnmsub mask3 intrinsicsCraig Topper2016-10-261-0/+4
| | | | | | | | | | | | Summary: Clang's intrinsic header currently tries to negate the third operand of a vfmadd mask3 in order to create vfmsub, but this fails isel. This patch adds scalar vfmsub and vfnmsub mask3 that we can use instead to avoid the negate. This is consistent with the packed instructions. Reviewers: igorb, delena Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25933 llvm-svn: 285173
* Cloning: Also clone global variable attached metadata.Peter Collingbourne2016-10-261-0/+5
| | | | llvm-svn: 285161
* [libFuzzer] simplify the code in TracePC::HandleTrace a bit moreKostya Serebryany2016-10-263-33/+18
| | | | llvm-svn: 285147
* [libFuzzer] simplify the code to print new PCsKostya Serebryany2016-10-264-16/+20
| | | | llvm-svn: 285145
* Utility functions for appending to llvm.used/llvm.compiler.used.Evgeniy Stepanov2016-10-255-99/+69
| | | | llvm-svn: 285143
* [libFuzzer] simplify the code in TracePC::HandleTraceKostya Serebryany2016-10-253-5/+9
| | | | llvm-svn: 285142
* [libFuzzer] add StandaloneFuzzTargetMain.c and a test for itKostya Serebryany2016-10-255-3/+62
| | | | llvm-svn: 285135
* [Sparc] Don't overlap variable-sized allocas with other stack variables.James Y Knight2016-10-251-3/+43
| | | | | | | | | | | | | | | | | | | | On SparcV8, it was previously the case that a variable-sized alloca might overlap by 4-bytes the last fixed stack variable, effectively because 92 (the number of bytes reserved for the register spill area) != 96 (the offset added to SP for where to start a DYNAMIC_STACKALLOC). It's not as simple as changing 96 to 92, because variables that should be 8-byte aligned would then be misaligned. For now, simply increase the allocation size by 8 bytes for each dynamic allocation -- wastes space, but at least doesn't overlap. As the large comment says, doing this more efficiently will require larger changes in llvm. Also adds some test cases showing that we continue to not support dynamic stack allocation and over-alignment in the same function. llvm-svn: 285131
* [codeview] support emitting indirect virtual base class informationBob Haarman2016-10-253-5/+13
| | | | | | | | | | | | | | | | Summary: Fixes PR28281. MSVC lists indirect virtual base classes in the field list of a class, using LF_IVBCLASS records. This change makes LLVM emit such records when processing DW_TAG_inheritance tags with the DIFlagVirtual and (newly introduced) DIFlagIndirect tags. Reviewers: rnk, ruiu, zturner Differential Revision: https://reviews.llvm.org/D25578 llvm-svn: 285130
* [DAGCombiner] Enable (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), ↵Simon Pilgrim2016-10-251-3/+3
| | | | | | -1)) combine for splatted vectors llvm-svn: 285129
* [PGO] Fix select instruction annotationRong Xu2016-10-251-4/+13
| | | | | | | | | | | | | | | | Summary: Select instruction annotation in IR PGO uses the edge count to infer the branch count. It's currently placed in setInstrumentedCounts() where no all the BB counts have been computed. This leads to wrong branch weights. Move the annotation after all BB counts are populated. Reviewers: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25961 llvm-svn: 285128
* [DAGCombiner] Enable srem(x.y) -> urem(x,y) combine for vectorsSimon Pilgrim2016-10-251-4/+2
| | | | | | SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927 llvm-svn: 285123
* [DAGCombiner] Enable sdiv(x.y) -> udiv(x,y) combine for vectorsSimon Pilgrim2016-10-251-4/+2
| | | | | | SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927 llvm-svn: 285118
* [InstCombine] Resubmit the combine of A->B->A BitCast and fix for pr27996Guozhi Wei2016-10-252-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original patch of the A->B->A BitCast optimization was reverted by r274094 because it may cause infinite loop inside compiler https://llvm.org/bugs/show_bug.cgi?id=27996. The problem is with following code xB = load (type B); xA = load (type A); +yA = (A)xB; B -> A +zAn = PHI[yA, xA]; PHI +zBn = (B)zAn; // A -> B store zAn; store zBn; optimizeBitCastFromPhi generates +zBn = (B)zAn; // A -> B and expects it will be combined with the following store instruction to another store zAn Unfortunately before combineStoreToValueType is called on the store instruction, optimizeBitCastFromPhi is called on the new BitCast again, and this pattern repeats indefinitely. optimizeBitCastFromPhi only generates BitCast for load/store instructions, only the BitCast before store can cause the reexecution of optimizeBitCastFromPhi, and BitCast before store can easily be handled by InstCombineLoadStoreAlloca.cpp. So the solution to the problem is if all users of a CI are store instructions, we should not do optimizeBitCastFromPhi on it. Then optimizeBitCastFromPhi will not be called on the new BitCast instructions. Differential Revision: https://reviews.llvm.org/D23896 llvm-svn: 285116
* revert: "Remove debug location from common tail when tail-merging"Robert Lougher2016-10-251-5/+2
| | | | | | | | This reverts r285093, as it caused unexpected buildbot failures on clang-ppc64le-linux, clang-ppc64be-linux, clang-ppc64be-linux-multistage and clang-ppc64be-linux-lnt. Failing test ubsan/TestCases/TypeCheck/vptr.cpp. llvm-svn: 285110
* [libFuzzer] when mutating based on CMP traces also try adding +/- 1 to the ↵Kostya Serebryany2016-10-253-11/+10
| | | | | | desired bytes. Add another test for use_cmp llvm-svn: 285109
* [InstCombine] Ensure that truncated int types are legal.Sanjay Patel2016-10-251-4/+2
| | | | | | | | | | Fixes the FIXMEs in D25952 and rL285075. Patch by bryant! Differential Revision: https://reviews.llvm.org/D25955 llvm-svn: 285108
* [AArch64] Adjust the cost model for Exynos M1.Evandro Menezes2016-10-251-1/+1
| | | | | | Modify the maximum jump table size. llvm-svn: 285106
* [APFloat] Make APFloat an interface class to the internal IEEEFloat. NFC.Tim Shen2016-10-251-372/+244
| | | | | | | | | | | | | | | | | | | | | Summary: The intention is to make APFloat an interface class, so that later I can add a second implementation class DoubleAPFloat to correctly implement PPCDoubleDouble semantic. The interface of IEEEFloat is not public, and can be simplified (currently it's exactly the same as the old APFloat), but that belongs to a separate patch. DoubleAPFloat should look like: class DoubleAPFloat { const fltSemantics *Semantics; std::unique_ptr<APFloat> APFloats; // Two heap-allocated APFloats. }; There is no functional change, nor public interface change. Reviewers: hfinkel, chandlerc, iteratee, echristo, kbarton Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D25536 llvm-svn: 285105
* Add option to specify minimum number of entries for jump tablesEvandro Menezes2016-10-251-3/+14
| | | | | | | | | | Add an option to allow easier experimentation by target maintainers with the minimum number of entries to create jump tables. Also clarify the name of the other existing option governing the creation of jump tables. Differential revision: https://reviews.llvm.org/D25883 llvm-svn: 285104
* Switch lowering: improve partitioning of jump tablesEvandro Menezes2016-10-251-14/+31
| | | | | | | | | | | When there's a tie between partitionings of jump tables, consider also cases that result in no jump tables, but in one or a few cases. The motivation is that many contemporary processors typically perform case switches fairly quickly. Differential revision: https://reviews.llvm.org/D25212 llvm-svn: 285099
* [LV] Sink scalar operands of predicated instructionsMatthew Simpson2016-10-251-13/+78
| | | | | | | | | | | | | When we predicate an instruction (div, rem, store) we place the instruction in its own basic block within the vectorized loop. If a predicated instruction has scalar operands, it's possible to recursively sink these scalar expressions into the predicated block so that they might avoid execution. This patch sinks as much scalar computation as possible into predicated blocks. We previously were able to sink such operands only if they were extractelement instructions. Differential Revision: https://reviews.llvm.org/D25632 llvm-svn: 285097
* Add -strip-nonlinetable-debuginfo capabilityMichael Ilseman2016-10-255-1/+338
| | | | | | | | | | | | | | | | | | | | | | | | This adds a new function to DebugInfo.cpp that takes an llvm::Module as input and removes all debug info metadata that is not directly needed for line tables, thus effectively stripping all type and variable information from the module. The primary motivation for this feature was the bitcode work flow (cf. http://lists.llvm.org/pipermail/llvm-dev/2016-June/100643.html for more background). This is not wired up yet, but will be in subsequent patches. For testing, the new functionality is exposed to opt with a -strip-nonlinetable-debuginfo option. The secondary use-case (and one that works right now!) is as a reduction pass in bugpoint. I added two new bugpoint options (-disable-strip-debuginfo and -disable-strip-debug-types) to control the new features. By default it will first attempt to remove all debug information, then only the type info, and then proceed to hack at any remaining MDNodes. Thanks to Adrian Prantl for stewarding this patch! llvm-svn: 285094
* Remove debug location from common tail when tail-mergingRobert Lougher2016-10-251-2/+5
| | | | | | | | | | | | | | The branch folding pass tail merges blocks into a common-tail. However, the tail retains the debug information from one of the original inputs to the merge (chosen randomly). This is a problem for sampled-based PGO, as hits on the common-tail will be attributed to whichever block was chosen, irrespective of which path was actually taken to the common-tail. This patch fixes the issue by nulling the debug location for the common-tail. Differential Revision: https://reviews.llvm.org/D25742 llvm-svn: 285093
* Fix 80-char violations. NFC.Michael Kuperstein2016-10-251-5/+10
| | | | llvm-svn: 285092
* [WebAssembly] Add immediate fields to call_indirect and memory operators.Dan Gohman2016-10-254-18/+26
| | | | | | | call_indirect, grow_memory, and current_memory now have immediate operands in the 0xd binary encoding. llvm-svn: 285085
* Move discriminator assignment to where it is used. (NFC)Dehao Chen2016-10-251-1/+1
| | | | llvm-svn: 285084
* [IndVarSimplify][Dwarf] When widening the IV increment, correctly set the ↵Andrea Di Biagio2016-10-251-0/+5
| | | | | | | | | | | | | | | debug loc. When indvars widened an induction variable, the debug location for the loop increment computation was incorrectly set equal to the debug loc of the loop latch terminator. This patch fixes the issue by propagating the correct location from the original loop increment instruction to the new widened increment. Differential Revision: https://reviews.llvm.org/D25872 llvm-svn: 285083
* Replace TimeValue by TimePoint in LegacyPassManager. NFC.Pavel Labath2016-10-251-5/+4
| | | | llvm-svn: 285081
* [EarlyCSE] Make MemorySSA memory dependency check more aggressive.Geoff Berry2016-10-251-16/+6
| | | | | | | | | | Now that MemorySSA keeps track of whether MemoryUses are optimized, use getClobberingMemoryAccess() to check MemoryUse memory dependencies since it should no longer be so expensive. This is a follow-up change to https://reviews.llvm.org/D25881 llvm-svn: 285080
* fix formatting; NFCSanjay Patel2016-10-251-13/+13
| | | | llvm-svn: 285078
* [SystemZ] Do not use LOC(G) for volatile loadsUlrich Weigand2016-10-251-1/+1
| | | | | | | | | | | | | | It is not safe to use LOAD ON CONDITION to implement access to a memory location marked "volatile", since the architecture leaves it unspecified whether or not an access happens if the condition is false. The current code already appears to care about that: def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>; Unfortunately, that "nonvolatile_load" operator is simply ignored by the CondUnaryRSY class, and there was no test to catch it. llvm-svn: 285077
* [InstCombine] add test and code comment to show potentially misguided icmp ↵Sanjay Patel2016-10-251-0/+3
| | | | | | trunc transform llvm-svn: 285075
* [X86][SSE] Add support for (V)PMOVSX* constant foldingSimon Pilgrim2016-10-251-13/+54
| | | | | | | | | | We already have (V)PMOVZX* combining support, this is the beginning of handling (V)PMOVSX* similarly - other combines in combineVSZext can be generalized in future patches. This unearthed an interesting bug in that we were generating illegal build vectors on 32-bit targets - it was proving difficult to create a test for it from PMOVZX, but it fired immediately with PMOVSX. I've created a more general form of the existing getConstVector to handle these cases - ideally this should be handled in non-target-specific code but I couldn't find an equivalent. Differential Revision: https://reviews.llvm.org/D25874 llvm-svn: 285072
* fix warningRafael Espindola2016-10-251-0/+1
| | | | llvm-svn: 285064
* [DAGCombine] Preserve shuffles when one of the vector operands is constantZvi Rackover2016-10-251-34/+75
| | | | | | | | | | | | | | | | | | | | Summary: Do *not* perform combines such as: vector_shuffle<4,1,2,3>(build_vector(Ud, C0, C1 C2), scalar_to_vector(X)) -> build_vector(X, C0, C1, C2) Keeping the shuffle allows lowering the constant build_vector to a materialized constant vector (such as a vector-load from the constant-pool or some other idiom). Reviewers: delena, igorb, spatel, mkuper, andreadb, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25524 llvm-svn: 285063
* Make the LTO comdat api more symbol table friendly.Rafael Espindola2016-10-251-2/+29
| | | | | | | | | | | | | | | | | | | | | | In an IR symbol table I would expect the comdats to be represented as: - A table of strings, one for each comdat name. - Each symbol has an optional index into that table. The natural api for accessing that would be InputFile: ArrayRef<StringRef> getComdatTable() const; Symbol: int getComdatIndex() const; This patch implements an API as close to that as possible. The implementation on top of the current IRObjectFile is a bit hackish, but should map just fine over a symbol table and is very convenient to use. llvm-svn: 285061
* Fix an unused warning in WebAssemblyInstPrinter with NDEBUG.Benjamin Kramer2016-10-251-0/+1
| | | | | | | | Patch by Sam McCall! Differential Revision: https://reviews.llvm.org/D25934 llvm-svn: 285055
* [AVX-512] Add support for creating SIGN_EXTEND_VECTOR_INREG and ↵Craig Topper2016-10-251-11/+39
| | | | | | | | | | | | | | ZERO_EXTEND_VECTOR_INREG for 512-bit vectors to support vpmovzxbq and vpmovsxbq. Summary: The one tricky thing about this is that the sign/zero_extend_inreg uses v64i8 as an input type which isn't legal without BWI support. Though the vpmovsxbq and vpmovzxbq instructions themselves don't require BWI. To support this we need to add custom lowering for ZERO_EXTEND_VECTOR_INREG with v64i8 input. This can mostly reuse the existing sign extend code with a couple checks for sign extend vs zero extend added. Reviewers: delena, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25594 llvm-svn: 285053
* GlobalDCE: Restore a statement accidentally removed in r285048.Peter Collingbourne2016-10-251-0/+1
| | | | llvm-svn: 285052
* MachineInstrBundle: Pass iterators to getBundle(Start|End); NFCMatthias Braun2016-10-252-3/+3
| | | | | | | | This is a function to go backwards in a block to find the first instruction in a bundle, so iterator is a more natural choice for parameter/return rather than a reference to a MachineInstruction. llvm-svn: 285051
* IR: Deduplicate getParent() functions on derived classes of GlobalValue into ↵Peter Collingbourne2016-10-252-16/+0
| | | | | | the base class. NFCI. llvm-svn: 285050
* [libFuzzer] simplify the code for use_cmp, also use the position hint when ↵Kostya Serebryany2016-10-259-102/+130
| | | | | | available, add a test llvm-svn: 285049
* GlobalDCE: Deduplicate code. NFCI.Peter Collingbourne2016-10-251-35/+18
| | | | llvm-svn: 285048
* [WebAssembly] Reorder load/store operands to match binary encoding.Dan Gohman2016-10-254-294/+296
| | | | | | | The p2align operand of a load/store is encoded before the offset operand; reorder the MachineInstr operands accordingly. llvm-svn: 285044
* [WebAssembly] Implement more WebAssembly binary encoding.Dan Gohman2016-10-2416-131/+126
| | | | | | | | | | | | This changes locals from being declared by the emitLocal hook in WebAssemblyTargetStreamer, rather than with an instruction. After exploring the infastructure in LLVM more, this seems to make more sense since declaring locals doesn't use an encoded opcode. This also adds more 0xd opcodes, type encodings, and miscellaneous binary encoding bits. llvm-svn: 285040
* CodeGen/Passes: Pass MachineFunction as functor arg; NFCMatthias Braun2016-10-243-13/+14
| | | | | | | | Passing a MachineFunction as argument is more natural and avoids an unnecessary round-trip through the logic determining the correct Subtarget because MachineFunction already has a reference anyway. llvm-svn: 285039
* Fix regression from my recent GlobalsAA fix.Eli Friedman2016-10-241-1/+3
| | | | | | | | | | | | | There are two fixes here: one, AnalyzeUsesOfPointer can't return false until it has checked all the uses of the pointer. Two, if a global uses another global, we have to assume the address of the first global escapes. Fixes https://llvm.org/bugs/show_bug.cgi?id=30707 . Differential Revision: https://reviews.llvm.org/D25798 llvm-svn: 285034
* [SelectionDAG] Update ComputeNumSignBits SRA/SHL handlers to accept scalar ↵Simon Pilgrim2016-10-241-6/+7
| | | | | | | | | | or vector splats Use isConstOrConstSplat helper. Also use APInt instead of getZExtValue directly to avoid out of range issues. llvm-svn: 285033
* Use MachineInstr::mop_iterator instead of MIOperands; NFCMatthias Braun2016-10-246-36/+36
| | | | | | | | (Const)?MIOperands is equivalent to the C++ style MachineInstr::mop_iterator. Use the latter for consistency except for a few callers of MIOperands::analyzePhysReg(). llvm-svn: 285029
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