diff options
| author | Saleem Abdulrasool <compnerd@compnerd.org> | 2016-10-31 22:12:37 +0000 |
|---|---|---|
| committer | Saleem Abdulrasool <compnerd@compnerd.org> | 2016-10-31 22:12:37 +0000 |
| commit | e1aa782bd073925dae4c3069e396bdd77e2199a1 (patch) | |
| tree | 30ac281c976b9b90ae7049c89ee184e4f9a0dfd0 /llvm/lib | |
| parent | 002af9bbcec16fea530d161b23cc2589fe0798b7 (diff) | |
| download | bcm5719-llvm-e1aa782bd073925dae4c3069e396bdd77e2199a1.tar.gz bcm5719-llvm-e1aa782bd073925dae4c3069e396bdd77e2199a1.zip | |
CodeGen: further loosen -O0 CG for WoA division
Generate the slowest possible codepath for noopt CodeGen. Even trying to be
clever with the negated jump can cause out-of-range jumps. Use a wide branch
instead. Although the code is modelled simplistically, the later optimizations
would recombine the branching into `cbz` if possible. This re-enables the
previous optimization as well as hopefully gives us working code in all cases.
Addresses PR30356!
llvm-svn: 285649
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 12f32472461..a87cf507f58 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -8593,12 +8593,20 @@ ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI, ContBB->splice(ContBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)), MBB->end()); ContBB->transferSuccessorsAndUpdatePHIs(MBB); - - BuildMI(*MBB, MI, DL, TII->get(ARM::tCBNZ)) - .addReg(MI.getOperand(0).getReg()) - .addMBB(ContBB); MBB->addSuccessor(ContBB); - BuildMI(*MBB, MI, DL, TII->get(ARM::t__brkdiv0)); + + MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock(); + BuildMI(TrapBB, DL, TII->get(ARM::t__brkdiv0)); + MF->push_back(TrapBB); + MBB->addSuccessor(TrapBB); + + AddDefaultPred(BuildMI(*MBB, MI, DL, TII->get(ARM::tCMPi8)) + .addReg(MI.getOperand(0).getReg()) + .addImm(0)); + BuildMI(*MBB, MI, DL, TII->get(ARM::t2Bcc)) + .addMBB(TrapBB) + .addImm(ARMCC::EQ) + .addReg(ARM::CPSR); MI.eraseFromParent(); return ContBB; |

