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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-10-25 20:56:42 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-10-25 20:56:42 +0000 |
| commit | 4ebb04510a9c656fa83e91aec43380f6edec1f56 (patch) | |
| tree | 55c1ec0de884c3613bbda8923dfc892a80925ae9 /llvm/lib | |
| parent | 8f29ea36c36291d66c2630e23e435bd75c3e491c (diff) | |
| download | bcm5719-llvm-4ebb04510a9c656fa83e91aec43380f6edec1f56.tar.gz bcm5719-llvm-4ebb04510a9c656fa83e91aec43380f6edec1f56.zip | |
[DAGCombiner] Enable sdiv(x.y) -> udiv(x,y) combine for vectors
SelectionDAG::SignBitIsZero (via SelectionDAG::computeKnownBits) has supported vectors since rL280927
llvm-svn: 285118
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 8f77ccd3c2f..daa0ea7afbd 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2317,10 +2317,8 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) { // If we know the sign bits of both operands are zero, strength reduce to a // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 - if (!VT.isVector()) { - if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) - return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1); - } + if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) + return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1); // fold (sdiv X, pow2) -> simple ops after legalize // FIXME: We check for the exact bit here because the generic lowering gives |
