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* Output MachO section names in the form SEGMENT,section.Benjamin Kramer2011-07-151-2/+2
| | | | llvm-svn: 135231
* Add support for 64 bit objects to MachOObjectFile.Benjamin Kramer2011-07-151-21/+77
| | | | | | - I don't see a better way than duplicating all the code. llvm-svn: 135229
* MachOObjectFile: Change isSectionText to return true for sections named ↵Benjamin Kramer2011-07-151-4/+3
| | | | | | text, not for load commands name __TEXT (which isn't the case in actual object files) llvm-svn: 135228
* Encode that we have a personality function.Bill Wendling2011-07-151-0/+3
| | | | llvm-svn: 135227
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-1476-175/+229
| | | | | | MCTargetDesc to prepare for next round of changes. llvm-svn: 135219
* * If we have an LSDA, we need to mark it in the encoding.Bill Wendling2011-07-141-1/+5
| | | | | | * The personality function should be encoded as an absolute pointer to the function. llvm-svn: 135215
* Refactor.Devang Patel2011-07-142-19/+9
| | | | llvm-svn: 135212
* Eliminate redundant LLVMContext argument.Devang Patel2011-07-142-9/+11
| | | | | | Improve DbgScope->dump() output. llvm-svn: 135207
* Undo r135191 (i.e. reapply Chris's patch. Now linker maps NamedMDNodes ↵Devang Patel2011-07-141-2/+3
| | | | | | first, so there is not any need to map DebugLoc). llvm-svn: 135205
* Link NamedMDNode before linking function bodies.Devang Patel2011-07-141-5/+5
| | | | llvm-svn: 135204
* ARM diagnostic when 's' suffix on mnemonic that can't set flags.Jim Grosbach2011-07-141-7/+9
| | | | | | | | For example, "mlss r0, r1, r2, r3". The MLS instruction does not have a flag-setting variant. llvm-svn: 135203
* * Redo the permutation encoding for frameless stacks to be more like what theBill Wendling2011-07-141-44/+73
| | | | | | | unwind library expects. * Comment the permutation encoding for frameless stacks. llvm-svn: 135202
* Add dump()Devang Patel2011-07-141-0/+16
| | | | llvm-svn: 135200
* Add OperandTypes for Thumb branch targets.Benjamin Kramer2011-07-141-0/+3
| | | | llvm-svn: 135199
* Port operand types for ARM and X86 over from EDIS to the .td files.Benjamin Kramer2011-07-143-1/+18
| | | | llvm-svn: 135198
* ARM MCRR/MCRR2 immediate operand range checking.Jim Grosbach2011-07-142-3/+3
| | | | llvm-svn: 135192
* revert r135172 until Devang and I figure out the right answer.Chris Lattner2011-07-141-3/+2
| | | | llvm-svn: 135191
* ARM MCR/MCR2 assembly parsing operand constraints.Jim Grosbach2011-07-142-8/+8
| | | | | | | The immediate operands are restricted to 0-7. Enforce that when parsing assembly. llvm-svn: 135189
* After type-system-rewrite branch update the Cpp backend to not use OpaqueType.Nicolas Geoffray2011-07-141-103/+46
| | | | llvm-svn: 135186
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-14131-469/+1244
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* simplify this logic now that GlobalAlias::isDeclaration is fixed.Chris Lattner2011-07-141-4/+2
| | | | llvm-svn: 135183
* Fix GlobalValue::isDeclaration() to always consider aliases to be definitions.Chris Lattner2011-07-141-3/+2
| | | | llvm-svn: 135182
* Check register class matching instead of width of type matchingEric Christopher2011-07-143-10/+15
| | | | | | | | | when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 llvm-svn: 135180
* Reorganize ARM assembler aliases.Jim Grosbach2011-07-141-14/+19
| | | | | | | | Consolidate the individual declarations together for ease of reference. This mirrors the organization in X86, as well, so is good for consistency. No functional change. llvm-svn: 135179
* Add LLVMConstNamedStruct to the C api to let its users create constantsRafael Espindola2011-07-141-0/+10
| | | | | | of named struct types. llvm-svn: 135178
* DebugLoc's don't hide any interesting types for TypeFinder to find.Chris Lattner2011-07-141-1/+1
| | | | llvm-svn: 135174
* manually copy debugloc over to a new instruction in clone() insteadChris Lattner2011-07-141-1/+3
| | | | | | | of calling getAllMetadata(). This is semantically identical, but doing it this way avoids unpacking the DebugLoc. llvm-svn: 135173
* Stop the ValueMapper from calling getAllMetadata, which unpacks DebugLoc intoChris Lattner2011-07-141-2/+3
| | | | | | | an MDNode. This saves a bunch of time and memory in the IR linker, e.g. when doing LTO of files with debug info. llvm-svn: 135172
* Add 256-bit load/store recognition and matching in several places.Bruno Cardoso Lopes2011-07-142-4/+74
| | | | llvm-svn: 135171
* Don't leak operands when putting them into a shift.Benjamin Kramer2011-07-141-1/+1
| | | | llvm-svn: 135169
* Update ARM Assembly of LDM/STM.Jim Grosbach2011-07-141-5/+8
| | | | | | | ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such. Update the parsing/encoding tests accordingly. llvm-svn: 135168
* add comments.Chris Lattner2011-07-141-1/+3
| | | | llvm-svn: 135164
* consolidate GlobalValue::isDeclaration into one Chris Lattner2011-07-141-8/+13
| | | | | | non-virtual function. llvm-svn: 135163
* code cleanupChris Lattner2011-07-141-20/+15
| | | | llvm-svn: 135157
* ARM ISB instruction assembly parsing.Jim Grosbach2011-07-142-3/+7
| | | | | | | The ISB instruction takes an optional operand, just like DMB/DSB. Typically only 'sy' is meaningful. llvm-svn: 135156
* Change Intrinsic::getDeclaration and friends to take an ArrayRef.Benjamin Kramer2011-07-149-23/+18
| | | | llvm-svn: 135154
* add a couple more missing C api, patch by Vitaly Lugovskiy!Chris Lattner2011-07-141-0/+8
| | | | llvm-svn: 135151
* Update XCoreRegisterInfo::eliminateFrameIndex() to handle DBG_VALUERichard Osborne2011-07-141-9/+17
| | | | | | instructions. llvm-svn: 135146
* Simplify some functions in the C API by using an ArrayRef to directly ↵Frits van Bommel2011-07-141-13/+3
| | | | | | reference the array passed to them instead of copying it to a std::vector. llvm-svn: 135145
* [VECTOR-SELECT]Nadav Rotem2011-07-143-3/+66
| | | | | | | | | | | During type legalization we often use the SIGN_EXTEND_INREG SDNode. When this SDNode is legalized during the LegalizeVector phase, it is scalarized because non-simple types are automatically marked to be expanded. In this patch we add support for lowering SIGN_EXTEND_INREG manually. This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements' flag. llvm-svn: 135144
* Add assertion for the chain value typeNadav Rotem2011-07-141-0/+10
| | | | llvm-svn: 135143
* add C api for hte new type system rewrite API. Patch by Vitaly Lugovskiy!Chris Lattner2011-07-141-0/+13
| | | | llvm-svn: 135132
* Unfortunately several files in MC are badly violating layering rule by usingEvan Cheng2011-07-148-16/+23
| | | | | | | | | TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are other cases of violations, but this is probably the worst. This patch is but one small step towards fixing this. 500 more steps to go. :-( llvm-svn: 135131
* Reapply r135121 with a fixed copy constructor.Jakob Stoklund Olesen2011-07-143-11/+70
| | | | | | | | | | | | | | | | | | | | | Original commit message: Count references to interference cache entries. Each InterferenceCache::Cursor instance references a cache entry. A non-zero reference count guarantees that the entry won't be reused for a new register. This makes it possible to have multiple live cursors examining interference for different physregs. The total number of live cursors into a cache must be kept below InterferenceCache::getMaxCursors(). Code generation should be unaffected by this change, and it doesn't seem to affect the cache replacement strategy either. llvm-svn: 135130
* Simplify.Devang Patel2011-07-141-13/+3
| | | | llvm-svn: 135127
* Don't emit a bit test if there is only one case the test can yield false. A ↵Benjamin Kramer2011-07-142-10/+13
| | | | | | simple SETNE is sufficient. llvm-svn: 135126
* Simplify and delay extracting DebugLoc elements, scope and InlinedAt, as ↵Devang Patel2011-07-143-18/+30
| | | | | | much as possible. llvm-svn: 135124
* Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-AEric Christopher2011-07-141-2/+10
| | | | | | Fixes rdar://9761830 llvm-svn: 135123
* Revert r135121 which broke a gcc-4.2 builder.Jakob Stoklund Olesen2011-07-143-70/+11
| | | | llvm-svn: 135122
* Count references to interference cache entries.Jakob Stoklund Olesen2011-07-143-11/+70
| | | | | | | | | | | | | | | | | Each InterferenceCache::Cursor instance references a cache entry. A non-zero reference count guarantees that the entry won't be reused for a new register. This makes it possible to have multiple live cursors examining interference for different physregs. The total number of live cursors into a cache must be kept below InterferenceCache::getMaxCursors(). Code generation should be unaffected by this change, and it doesn't seem to affect the cache replacement strategy either. llvm-svn: 135121
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