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* [ICP] Expose unconditional call promotion interfaceMatthew Simpson2017-12-201-77/+178
| | | | | | | | | | | | | | | | | | | | | | | This patch modifies the indirect call promotion utilities by exposing and using an unconditional call promotion interface. The unconditional promotion interface (i.e., call promotion without creating an if-then-else) can be used if it's known that an indirect call has only one possible callee. The existing conditional promotion interface uses this unconditional interface to promote an indirect call after it has been versioned and placed within the "then" block. A consequence of unconditional promotion is that the fix-up operations for phi nodes in the normal destination of invoke instructions are changed. This is necessary because the existing implementation assumed that an invoke had been versioned, creating a "merge" block where a return value bitcast could be placed. In the new implementation, the edge between a promoted invoke's parent block and its normal destination is split if needed to add a bitcast for the return value. If the invoke is also versioned, the phi node merging the return value of the promoted and original invoke instructions is placed in the "merge" block. Differential Revision: https://reviews.llvm.org/D40751 llvm-svn: 321210
* [X86] Remove zext from vXi32 to vXi64 on indices of gather/scatter ↵Craig Topper2017-12-201-0/+17
| | | | | | | | instructions if we can prove the pre-extended value is positive. Gather/scatter can implicitly sign extend from i32->i64 on indices. So if we know the sign bit of the input to a zext is 0 we can use the implicit extension. llvm-svn: 321209
* DAG: Tolerate non-MemSDNodes for OPC_RecordMemRefMatt Arsenault2017-12-201-8/+24
| | | | | | | | | | | | | | | | | | | | When intrinsics are allowed to have mem operands, there are two ways this can happen. First is an intrinsic that is marked has having a mem operand, but is not handled by getTgtMemIntrinsic. The second way can occur even for intrinsics which do not have a mem operand. It seems the selector table does some kind of sorting based on the opcode, and the mem ref recording can happen in the same scope for intrinsics that both do and do not have mem refs. I haven't been able to figure out exactly why this happens (although it happens even with the matcher optimizations disabled). I'm not sure if it's worth trying to avoid hitting this for these nodes since I think it's still reasonable to handle this in case getTgtMemIntrinic is not implemented. llvm-svn: 321208
* [PowerPC] Added an assert to make sure that the MBBI iterator is valid.Stefan Pintilie2017-12-201-3/+3
| | | | | | | | | | The function createTailCallBranchInstr assumes that the iterator MBBI is valid. However, only one use of MBBI is guarded in the function. Fix this by adding an assert. Differential Revision: https://reviews.llvm.org/D41358 llvm-svn: 321205
* [DAG] Fix condition on overlapping store check.Nirav Dave2017-12-201-2/+2
| | | | | | | Prevent overlapping store elision when overlapping store is pre-inc/dec as analysis is wrong in these cases. llvm-svn: 321204
* [hwasan] Implement -fsanitize-recover=hwaddress.Evgeniy Stepanov2017-12-201-7/+18
| | | | | | | | | | | | Summary: Very similar to AddressSanitizer, with the exception of the error type encoding. Reviewers: kcc, alekseyshl Subscribers: cfe-commits, kubamracek, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D41417 llvm-svn: 321203
* [AMDGPU, AsmParser] Enable the mnemonic spell corrector.Matt Arsenault2017-12-201-2/+15
| | | | | | Patch by Dmitry Venikov llvm-svn: 321202
* [X86] Implement the fusing of MUL+SUBADD to FMSUBADDCraig Topper2017-12-201-21/+48
| | | | | | | | | | This patch turns shuffles of fadd/fsub with fmul into fmsubadd. Patch by Dmitry Venikov Differential Revision: https://reviews.llvm.org/D40335 llvm-svn: 321200
* [PGO] Function section hotness prefix should look at all blocksTeresa Johnson2017-12-202-30/+43
| | | | | | | | | | | | | | | | | | | | Summary: The function section prefix for PGO based layout (e.g. hot/unlikely) should look at the hotness of all blocks not just the entry BB. A function with a cold entry but a very hot loop should be placed in the hot section, for example, so that it is located close to other hot functions it may call. For SamplePGO it was already looking at the branch weights on calls, and I made that code conditional on whether this is SamplePGO since it was essentially a noop for instrumentation PGO anyway. Reviewers: davidxl Subscribers: eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D41395 llvm-svn: 321197
* [InstCombine] Add debug location to new caller.Florian Hahn2017-12-201-0/+1
| | | | | | | | | | Reviewers: rnk, aprantl, majnemer Reviewed By: aprantl Differential Revision: https://reviews.llvm.org/D414 llvm-svn: 321191
* Revert r320548:[SLP] Vectorize jumbled memory loadsMohammad Shahid2017-12-202-266/+83
| | | | llvm-svn: 321181
* Add optional SelectionDAG* parameter to SValue::dump and SDValue::dumprKrzysztof Parzyszek2017-12-201-4/+4
| | | | | | | | | These functions simply call their counterparts in the associated SDNode, which do take an optional SelectionDAG. This change makes the legalization debug trace a little easier to read, since target-specific nodes will now have their names shown instead of "Unknown node #123". llvm-svn: 321180
* [NVPTX] Initial adaptation of MCAsmStreamer/MCTargetStreamer for debug info ↵Alexey Bataev2017-12-202-14/+55
| | | | | | | | | | | | | | | | | | | | | in Cuda. Summary: Initial changes in interfaces of MCAsmStreamer/MCTargetStreamer for correct debug info emission for Cuda. 1. PTX foramt does not support `.ascii` directives. Added the ability to nullify it. 2. The initial function label must follow the first debug `.loc` directive, not be followed by. 3. DWARF sections must be enclosed in braces. Reviewers: hfinkel, probinson, jlebar, rafael, echristo Subscribers: sdardis, nemanjai, llvm-commits, aprantl Differential Revision: https://reviews.llvm.org/D40033 llvm-svn: 321178
* [Hexagon] Adjust the value type for BCvt in LowerFormalArgumentsKrzysztof Parzyszek2017-12-201-2/+8
| | | | llvm-svn: 321177
* [LV] Remove unnecessary DoExtraAnalysis guard (silent bug)Florian Hahn2017-12-201-2/+2
| | | | | | | | | | | | | | canVectorize is only checking if the loop has a normalized pre-header if DoExtraAnalysis is true. This doesn't make sense to me because reporting analysis information shouldn't alter legality checks. This is probably the result of a last minute minor change before committing (?). Patch by Diego Caballero. Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D40973 llvm-svn: 321172
* Trivial commit to force LLVM to run TableGen for Mips target afterSander de Smalen2017-12-201-1/+1
| | | | | | | | | | a change to the AsmMatcherEmitter, and should fix the buildbot failure on llvm-clang-x86_64-expensive-checks-win. The issue is also described here: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119617.html llvm-svn: 321170
* [TargetParser] Check size before accessing architecture version.Florian Hahn2017-12-201-2/+2
| | | | | | | | | | | | | | | | | | Summary: This fixes a crash when invalid -march options like `armv` are provided. Based on a patch by Will Lovett. Reviewers: rengolin, samparker, mcrosier Reviewed By: samparker Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41429 llvm-svn: 321166
* [ARM GlobalISel] Fix assertion in RegBankSelectDiana Picus2017-12-202-1/+42
| | | | | | | | | | | | | | | | | | | | We get an assertion in RegBankSelect for code along the lines of my_32_bit_int = my_64_bit_int, which tends to translate into a 64-bit load, followed by a G_TRUNC, followed by a 32-bit store. This appears in a couple of places in the test-suite. At the moment, the legalizer doesn't distinguish between integer and floating point scalars, so a 64-bit load will be marked as legal for targets with VFP, and so will the rest of the sequence, leading to a slightly bizarre G_TRUNC reaching RegBankSelect. Since the current support for 64-bit integers is rather immature, this patch works around the issue by explicitly handling this case in RegBankSelect and InstructionSelect. In the future, we may want to revisit this decision and make sure 64-bit integer loads are narrowed before reaching RegBankSelect. llvm-svn: 321165
* [ARM] Lower unsigned saturation to USAT Florian Hahn2017-12-204-7/+35
| | | | | | | | | | | | | | | | | Summary: Implement lower of unsigned saturation on an interval [0, k] where k + 1 is a power of two using USAT instruction in a similar way to how [~k, k] is lowered using SSAT on ARM models that supports it. Patch by Marten Svanfeldt Reviewers: t.p.northover, pbarrio, eastig, SjoerdMeijer, javed.absar, fhahn Reviewed By: fhahn Subscribers: fhahn, aemerson, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D41348 llvm-svn: 321164
* [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2Sander de Smalen2017-12-205-8/+247
| | | | | | | | | | | This patch resubmits the SVE ZIP1/ZIP2 patch series consisting of of r320992, r320986, r320973, and r320970 by reverting https://reviews.llvm.org/rL321024. The issue that caused r321024 has been addressed in https://reviews.llvm.org/rL321158, so this patch-series should be safe to resubmit. llvm-svn: 321163
* AArch64: fix one more place movi.2d could be created.Tim Northover2017-12-201-0/+14
| | | | | | Somehow got missed out of r320965. llvm-svn: 321162
* Give up on array allocas in getPointerDereferenceableBytesBjorn Steinbrink2017-12-201-4/+2
| | | | | | | | | | | | | | | Summary: As suggested by Eli Friedman, don't try to handle array allocas here, because of possible overflows, instead rely on instcombine converting them to allocations of array types. Reviewers: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41398 llvm-svn: 321159
* [AArch64] Asm: Fix parsing of register aliases that have a name starting ↵Sander de Smalen2017-12-201-19/+11
| | | | | | | | | | | | | | | | with 'z' Summary: This fixes an issue as identified by @rnk in https://reviews.llvm.org/rL321029. Reviewers: rnk, fhahn, rengolin, efriedma, echristo, olista01 Reviewed By: rnk, fhahn Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits, rnk Differential Revision: https://reviews.llvm.org/D41382 llvm-svn: 321158
* [AArch64] CCSIDR2 system registerSam Parker2017-12-201-0/+3
| | | | | | | | | | Implement the 'Current Cache Size' register that has been introduced as part of the Armv8.3 architecture. I originally missed this, and (hopefully) should be the final patch for assembler support. Differential Revision: https://reviews.llvm.org/D41396 llvm-svn: 321155
* [X86] Optimize sign extends on index operand to gather/scatter to not sign ↵Craig Topper2017-12-201-26/+24
| | | | | | | | | | extend past i32. The gather instruction will implicitly sign extend to the pointer width, we don't need to further extend it. This can prevent unnecessary splitting in some cases. There's still an issue that lowering on non-VLX can introduce another sign extend that doesn't get combined with shifts from a lowered sign_extend_inreg. llvm-svn: 321152
* [AArch64] Implement stack probing for windowsMartin Storsjo2017-12-201-9/+77
| | | | | | Differential Revision: https://reviews.llvm.org/D41131 llvm-svn: 321150
* [X86] Add a missing return to combineGatherScatter after sucessful combine.Craig Topper2017-12-201-0/+1
| | | | | | Not sure how to test this cause I think the worst that happens is that we don't revisit the node a second time to look for additional combines. We used UpdateNodeOperands so the updating the DAG work was already done. llvm-svn: 321148
* [PowerPC] fix a bug in redundant compare eliminationHiroshi Inoue2017-12-201-5/+13
| | | | | | | | | | This patch fixes a bug in the redundant compare elimination reported in https://reviews.llvm.org/rL320786 and re-enables the optimization. The redundant compare elimination assumes that we can replace signed comparison with unsigned comparison for the equality check. But due to the difference in the sign extension behavior we cannot change the opcode if the comparison is against an immediate and the most significant bit of the immediate is one. Differential Revision: https://reviews.llvm.org/D41385 llvm-svn: 321147
* [memcpyopt] Teach memcpyopt to optimize across basic blocksDan Gohman2017-12-202-19/+57
| | | | | | | | | | | | | | | | | This teaches memcpyopt to make a non-local memdep query when a local query indicates that the dependency is non-local. This notably allows it to eliminate many more llvm.memcpy calls in common Rust code, often by 20-30%. This is r319482 and r319483, along with fixes for PR35519: fix the optimization that merges stores into memsets to preserve cached memdep info, and fix memdep's non-local caching strategy to not assume that larger queries are always more conservative than smaller ones. Fixes PR28958 and PR35519. Differential Revision: https://reviews.llvm.org/D40802 llvm-svn: 321138
* [X86] Remove code from combineSext that looks for MVT::i1 after operation ↵Craig Topper2017-12-201-7/+1
| | | | | | | | legalization which can never happen. Type legalization guarantees this to be impossible since MVT::i1 isn't a legal type. llvm-svn: 321132
* [WebAssembly] Disable tee_local optimizations when targeting the ELF ABI.Dan Gohman2017-12-201-1/+9
| | | | | | | These optimizations depend on the ExplicitLocals pass to lower TEE instructions, which is disabled in the ELF ABI, so disable them too. llvm-svn: 321131
* [WebAssembly] Remove an obsolete comment.Dan Gohman2017-12-201-2/+1
| | | | llvm-svn: 321127
* Revert "Fix faulty assertion in debug info"Adrian McCarthy2017-12-192-4/+2
| | | | | | This reverts commit e32def3f7ebe1136b7038336eff56a415a962bf2. llvm-svn: 321125
* Fix faulty assertion in debug infoAdrian McCarthy2017-12-192-2/+4
| | | | | | | | | | | | | | It appears the code uses nullptr to represent a void type in debug metadata, which led to an assertion failure when building DeltaAlgorithm.cpp with a self-hosted clang on Windows. I'm not sure why/if the problem was Windows-specific. Fixes bug https://bugs.llvm.org/show_bug.cgi?id=35543 Differential Revision: https://reviews.llvm.org/D41264 llvm-svn: 321122
* [X86] Add an assert to indicate that there is only once specific VT allowed ↵Craig Topper2017-12-191-0/+2
| | | | | | | | at a certain point in LowerMULH. Helps with code readability a little. llvm-svn: 321118
* Silence a bunch of implicit fallthrough warningsAdrian Prantl2017-12-1916-7/+21
| | | | llvm-svn: 321114
* [CodeGen] Move printing MO_BlockAddress operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-192-44/+42
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 321113
* [CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-192-9/+4
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 321112
* [CodeGen] Move printing MO_IntrinsicID operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-192-15/+5
| | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. Also add support for printing with a null TargetIntrinsicInfo and no MachineFunction. llvm-svn: 321111
* [CodeGen] Move printing MO_FPImmediate operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-192-26/+2
| | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. llvm-svn: 321110
* [CodeGen] Refactor printOffset from MO and MIRPrinterFrancis Visoiu Mistrih2017-12-192-29/+16
| | | | llvm-svn: 321109
* [CGP] Format. NFCHaicheng Wu2017-12-191-1/+1
| | | | | | Clang-format. llvm-svn: 321107
* TargetLoweringBase: Fix darwinHasSinCos()Matthias Braun2017-12-191-1/+4
| | | | | | | | Another followup to my refactoring in r321036: Turns out we can end up with an x86 darwin target that is not macos (simulator triples can look like i386-apple-ios) so we need the x86/32bit check in all cases. llvm-svn: 321104
* [AMDGPU] Turn off MergeConsecutiveStores() before Instruction Selection for ↵Mark Searles2017-12-191-0/+10
| | | | | | | | AMDGPU. Commit dbbb6c5fc3642987430866dffdf710df4f616ac7 turned on MergeConsecutiveStores() before Instruction Selection for all targets. Enough AMDGPU compiles go into an infinite loop ( MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges; MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off until the issues can be addressed. Differential Revision: https://reviews.llvm.org/D41377 llvm-svn: 321100
* [SeparateConstOffsetFromGEP] Fix a typo. NFC.Haicheng Wu2017-12-191-1/+1
| | | | | | do CSE for to => do CSE to llvm-svn: 321098
* [GlobalISel][Legalizer] Fix crash when trying to lower G_FNEG of fp128 types.Amara Emerson2017-12-191-0/+3
| | | | | | | | | This doesn't add legalizer support, just prevents crashing so that we can gracefully fall back to SDAG. Fixes PR35690. llvm-svn: 321091
* [DAG] Elide overlapping storeNirav Dave2017-12-191-21/+21
| | | | | | | | | | | | | | | | | Summary: Extend overlapping store elision to handle overwrites of stores by larger stores. Nontemporal tests have been modified to add memory dependencies to prevent store elision. Reviewers: craig.topper, rnk, t.p.northover Subscribers: javed.absar, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D40969 llvm-svn: 321089
* [X86][AVX512] Attempt target shuffle combining to different types instead of ↵Simon Pilgrim2017-12-191-15/+9
| | | | | | | | | | early-out We try to prevent shuffle combining to value types that would stop the folding of masked operations, but by just returning early, we were failing to try different shuffle types. The TODOs are all still relevant here to improve codegen but we're lacking test examples. llvm-svn: 321085
* [CodeGen] Move printing MO_CFIIndex operands to MachineOperand::printFrancis Visoiu Mistrih2017-12-192-120/+125
| | | | | | | | | | Work towards the unification of MIR and debug output by refactoring the interfaces. Before this patch we printed "<call frame instruction>" in the debug output. llvm-svn: 321084
* [CFGVPrinter] Fix -dot-cfg-onlyFrancis Visoiu Mistrih2017-12-191-4/+4
| | | | | | The refactoring in r281640 made -dot-cfg-only ignore the "-only" part. llvm-svn: 321079
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