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* [X86] Support folding to andnps with SSE1 only.Craig Topper2017-11-251-1/+4
| | | | | | With SSE1 only, we emit FAND and FXOR nodes for v4f32. llvm-svn: 318968
* [X86] Add some early DAG combines to turn v4i32 AND/OR/XOR into ↵Craig Topper2017-11-251-6/+31
| | | | | | | | | | FAND/FOR/FXOR whe only SSE1 is available. v4i32 isn't a legal type with sse1 only and would end up getting scalarized otherwise. This isn't completely ideal as it doesn't handle cases like v8i32 that would get split to v4i32. But it at least helps with code written using the clang intrinsic header. llvm-svn: 318967
* Recommit r318963 "[APInt] Don't print debug messages from the APInt knuth ↵Craig Topper2017-11-241-0/+10
| | | | | | | | | | | | | | division algorithm by default" The previous commit had the condition in the do/while backwards. Debug builds currently print out low level details of the Knuth division algorithm when -debug is used. This information isn't useful in most cases and just adds noise to the log. This adds a new preprocessor flag to enable the prints in the knuth division code in APInt. Differential Revision: https://reviews.llvm.org/D40404 llvm-svn: 318966
* [X86] Prevent using X * rsqrt(X) to approximate sqrt when only sse1 is enabled.Craig Topper2017-11-241-1/+4
| | | | | | | | This optimization can occur after type legalization and emit a vselect with v4i32 type. But that type is not legal with sse1. This ultimately gets scalarized by the second type legalization that runs after vector op legalization, but that's really intended to handle the scalar types that might be introduced by legalizing vector ops. For now just stop this from happening by disabling the optimization with sse1. llvm-svn: 318965
* Revert 318963 "[APInt] Don't print debug messages from the APInt knuth ↵Craig Topper2017-11-241-10/+0
| | | | | | | | division algorithm by default" I seem to have botched the logic when switching to push_macro llvm-svn: 318964
* [APInt] Don't print debug messages from the APInt knuth division algorithm ↵Craig Topper2017-11-241-0/+10
| | | | | | | | | | | | by default Debug builds currently print out low level details of the Knuth division algorithm when -debug is used. This information isn't useful in most cases and just adds noise to the log. This adds a new preprocessor flag to enable the prints in the knuth division code in APInt. Differential Revision: https://reviews.llvm.org/D40404 llvm-svn: 318963
* [CodeGenPrepare] Check that erased sunken address are not reusedSimon Dardis2017-11-241-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | CodeGenPrepare sinks address computations from one basic block to another and attempts to reuse address computations that have already been sunk. If the same address computation appears twice with the first instance as an operand of a load whose result is an operand to a simplifable select, CodeGenPrepare simplifies the select and recursively erases the now dead instructions. CodeGenPrepare then attempts to use the erased address computation for the second load. Fix this by erasing the cached address value if it has zero uses before looking for the address value in the sunken address map. This partially resolves PR35209. Thanks to Alexander Richardson for reporting the issue! This fixed version relands r318032 which was reverted in r318049 due to sanitizer buildbot failures. Reviewers: john.brawn Differential Revision: https://reviews.llvm.org/D39841 llvm-svn: 318956
* [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16Dmitry Preobrazhensky2017-11-241-2/+18
| | | | | | | | | | See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629 Reviewers: artem.tamazov, SamWot, arsenm Differential Revision: https://reviews.llvm.org/D39488 llvm-svn: 318955
* Make helpers static. NFC.Benjamin Kramer2017-11-244-12/+14
| | | | llvm-svn: 318953
* [CGP] Make optimizeMemoryInst able to combine more kinds of ExtAddrMode fieldsJohn Brawn2017-11-241-12/+94
| | | | | | | | | | | | | This patch extends the recent work in optimizeMemoryInst to make it able to combine more ExtAddrMode fields than just the BaseReg. This fixes some benchmark regressions introduced by r309397, where GVN PRE is hoisting a getelementptr such that it can no longer be combined into the addressing mode of the load or store that uses it. Differential Revision: https://reviews.llvm.org/D38133 llvm-svn: 318949
* [mips] Set microMIPS ASE flagAleksandar Beserminji2017-11-242-1/+4
| | | | | | | | | | This patch fixes an issue where microMIPS ASE flag is not set when a function has micromips attribute or when .set micromips directive is used. Differential Revision: https://reviews.llvm.org/D40316 llvm-svn: 318948
* [AMDGPU][MC][GFX9] Added support of 'inst_offset' modifier for compatibility ↵Dmitry Preobrazhensky2017-11-241-2/+5
| | | | | | | | | | | | with SP3 See bug 35329: https://bugs.llvm.org//show_bug.cgi?id=35329 Reviewers: arsenm, vpykhtin, artem.tamazov Differential Revision: https://reviews.llvm.org/D40350 llvm-svn: 318947
* [X86] Don't invert NewCC variable while processing the jcc/setcc/cmovcc ↵Craig Topper2017-11-231-7/+9
| | | | | | | | | | instructions in optimizeCompareInstr. The NewCC variable is calculated outside of the loop that processes jcc/setcc/cmovcc instructions. If we invert it during the loop it can cause an incorrect value to be used by a later iteration. Instead only read it during the loop and use a new variable to store the possibly inverted value. Fixes PR35399. llvm-svn: 318934
* [X86] Teach isel that X86ISD::CMPM_RND zeros the upper bits of the mask ↵Craig Topper2017-11-232-1/+3
| | | | | | register. llvm-svn: 318933
* [X86] Remove some unneeded opcodes from getVectorMaskingNode. NFCCraig Topper2017-11-231-3/+0
| | | | | | We never reach here with these opcodes. llvm-svn: 318932
* [X86] Add X86ISD::CMPM_RND to getVectorMaskingNode to select ISD::AND ↵Craig Topper2017-11-231-0/+1
| | | | | | | | instead of ISD::VSELECT A later DAG combine will turn the VSELECT into an AND, but we have the other mask compare opcodes here so add this one too. llvm-svn: 318931
* [X86] Remove some dead code leftover from when i1 was a legal type. NFCICraig Topper2017-11-231-22/+3
| | | | llvm-svn: 318930
* [X86] Remove some dead code. NFCCraig Topper2017-11-231-4/+2
| | | | | | AVX512 code never reaches here so we don't need to handle X86ISD::CMPM as an opcode. llvm-svn: 318929
* MSan: remove an unnecessary cast. NFC for userspace instrumenetation.Alexander Potapenko2017-11-231-3/+3
| | | | llvm-svn: 318923
* [X86][SSE] Use (V)PHMINPOSUW for vXi16 SMAX/SMIN/UMAX/UMIN horizontal ↵Simon Pilgrim2017-11-235-7/+77
| | | | | | | | | | | | | | reductions (PR32841) (V)PHMINPOSUW determines the UMIN element in an v8i16 input, with suitable bit flipping it can also be used for SMAX/SMIN/UMAX cases as well. This patch matches vXi16 SMAX/SMIN/UMAX/UMIN horizontal reductions and reduces the input down to a v8i16 vector before calling (V)PHMINPOSUW. A later patch will use this for v16i8 reductions as well (PR32841). Differential Revision: https://reviews.llvm.org/D39729 llvm-svn: 318917
* [ARM GlobalISel] Support G_FDIV for s32 and s64Diana Picus2017-11-233-3/+8
| | | | | | | | | | | | TableGen already generates code for selecting a G_FDIV, so we only need to add a test. For the legalizer and reg bank select, we do the same thing as for the other floating point binary operations: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318915
* [ARM GlobalISel] Support G_FMUL for s32 and s64Diana Picus2017-11-233-3/+8
| | | | | | | | | | | TableGen already generates code for selecting a G_FMUL, so we only need to add a test for that part. For the legalizer and reg bank select, we do the same thing as the other floating point binary operators: either mark as legal if we have a FP unit or lower to a libcall, and map to the floating point registers. llvm-svn: 318910
* [mips] Use the delay slot filler to convert branches for microMIPSR6.Simon Dardis2017-11-231-10/+8
| | | | | | | | | | | | | | | | | | The MIPS delay slot filler converts delay slot branches into compact forms for the MIPS ISAs which support them. For branches that compare (in)equality with with zero, it converts them into branches with implict zero register operands. These branches have a slightly greater range than normal two register operands branches. Changing the branches at this point in the pipeline offers the long branch pass the ability to mark better judgements if a long branch sequence is required. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D40314 llvm-svn: 318908
* [x86][icelake]BITALGCoby Tayree2017-11-235-0/+45
| | | | | | | | | | 2/3 vpshufbitqmb encoding 3/3 vpshufbitqmb intrinsics Differential Revision: https://reviews.llvm.org/D40222 llvm-svn: 318904
* [MSan] Move the access address check before the shadow access for that addressAlexander Potapenko2017-11-231-2/+1
| | | | | | | | | | | | MSan used to insert the shadow check of the store pointer operand _after_ the shadow of the value operand has been written. This happens to work in the userspace, as the whole shadow range is always mapped. However in the kernel the shadow page may not exist, so the bug may cause a crash. This patch moves the address check in front of the shadow access. llvm-svn: 318901
* [IRCE][NFC] Add no wrap flags to no-wrapping SCEV calculationMax Kazantsev2017-11-231-2/+3
| | | | | | | | | In a lambda where we expect to have result within bounds, add respective `nsw/nuw` flags to help SCEV just in case if it fails to figure them out on its own. Differential Revision: https://reviews.llvm.org/D40168 llvm-svn: 318898
* Add backend name to AVR Target to enable runtime info to be fed back into ↵Leslie Zhai2017-11-231-1/+1
| | | | | | TableGen llvm-svn: 318895
* [X86] Turn an if condition that should always be true into an assert. NFCICraig Topper2017-11-231-44/+43
| | | | | | If Values.size() == 0, we should have returned 0 or undef earlier. If it was 1, it's a splat and we already handled that too. llvm-svn: 318894
* [X86] Remove unnecessary check for is128BitVector. NFCCraig Topper2017-11-231-1/+1
| | | | | | 256 and 512 bit vectors were picked off earlier in the function. Lots of code between there and here already assumed 128-bit vectors. llvm-svn: 318893
* [X86] Simplify some bitmasking and use llvm_unreachable to mark an ↵Craig Topper2017-11-231-2/+2
| | | | | | impossible case. NFC llvm-svn: 318892
* [X86] Remove a ternary operator that can only ever be false. NFCCraig Topper2017-11-231-2/+1
| | | | | | We are checking for AVX512 in an SSE1 only block. llvm-svn: 318891
* [NFC] CodeGen: Handle shift amount type in DAGTypeLegalizer::SplitIntegerYaxun Liu2017-11-232-13/+9
| | | | | | | | | | | | | | | | This patch reverts change to X86TargetLowering::getScalarShiftAmountTy in rL318727 and move the logic to DAGTypeLegalizer::SplitInteger. The reason is that getScalarShiftAmountTy returns a shift amount type that is suitable for common use cases in CodeGen. DAGTypeLegalizer::SplitInteger is a rare situation which requires a shift amount type larger than what getScalarShiftAmountTy. In this case, it is more reasonable to do special handling of shift amount type in DAGTypeLegalizer::SplitInteger only. If similar situations arises the logic may be moved to a separate function. Differential Revision: https://reviews.llvm.org/D40320 llvm-svn: 318890
* [AArch64] Adjust the cost model for Exynos M1 and M2Evandro Menezes2017-11-221-12/+17
| | | | | | Fix the modeling of some loads and stores. llvm-svn: 318884
* IR printing improvement for loop passesFedor Sergeev2017-11-221-0/+19
| | | | | | | | | | | | | | | | | | | Summary: Loop-pass printing is somewhat deficient since it does not provide the context around the loop (e.g. preheader). This context information becomes pretty essential when analyzing transformations that move stuff out of the loop. Extending printLoop to cover preheader and exit blocks (if any). Reviewers: sanjoy, silvas, weimingz Reviewed By: sanjoy Subscribers: apilipenko, skatkov, llvm-commits Differential Revision: https://reviews.llvm.org/D40246 llvm-svn: 318878
* [Hexagon] Implement buildVector32 and buildVector64 as utility functionsKrzysztof Parzyszek2017-11-222-133/+146
| | | | | | | | | Change LowerBUILD_VECTOR to use those functions. This commit will tempora- rily affect constant vector generation (it will generate constant-extended values instead of non-extended combines), but the code for the general case should be better. The constant selection part will be fixed later. llvm-svn: 318877
* [Hexagon] Add patterns to select A2_combine_ll and its variantsKrzysztof Parzyszek2017-11-221-0/+10
| | | | llvm-svn: 318876
* [Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek2017-11-222-3/+3
| | | | llvm-svn: 318875
* [X86] Support v32i16/v64i8 CTLZ using lookup table.Craig Topper2017-11-221-8/+18
| | | | | | Had to tweak the setcc's used by the code to use a vXi1 result type with a sign extend back to vector size. llvm-svn: 318871
* [X86] Move the BITALG setOperationAction code into the hasBWI section to ↵Craig Topper2017-11-221-5/+6
| | | | | | match what is done for VPOPCNTDQ in the AVX512F block. NFC llvm-svn: 318870
* [X86] Sink the MGATHER setOperationActions for AVX2 into the AVX block where ↵Craig Topper2017-11-221-7/+6
| | | | | | most of the rest of the AVX2 legalization lives. llvm-svn: 318869
* Allow TempFile::discard to be called twice.Rafael Espindola2017-11-221-0/+6
| | | | | | | | | | We already allowed keep+discard. It is important to be able to discard a temporary if a rename fail. It is also convenient as it allows the use of RAII for discarding. Allow discarding twice for similar reasons. llvm-svn: 318867
* CachePruning: Allow limiting the number of files in the cache directory.Peter Collingbourne2017-11-221-20/+30
| | | | | | | | | | | The default limit is 1000000 but it can be configured with a cache policy. The motivation is that some filesystems (notably ext4) have a limit on the number of files that can be contained in a directory (separate from the inode limit). Differential Revision: https://reviews.llvm.org/D40327 llvm-svn: 318857
* [DwarfDump] -debug-line=offset applies to .dwo too.Paul Robinson2017-11-221-1/+3
| | | | llvm-svn: 318856
* [X86] Spell penryn correctly in some comments. NFCCraig Topper2017-11-221-3/+3
| | | | llvm-svn: 318855
* [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argumentYaxun Liu2017-11-221-2/+3
| | | | | | | | | | | SITargetLowering::LowerCall uses dummy pointer info for byval argument, which causes flat load instead of buffer load. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40040 llvm-svn: 318844
* [DebugInfo] Dump a .debug_line section, including line-number program,Paul Robinson2017-11-222-5/+18
| | | | | | | | without any compile units. Differential Revision: https://reviews.llvm.org/D40114 llvm-svn: 318842
* [DWARFv5] Support DW_FORM_strp in the .debug_line.dwo header.Paul Robinson2017-11-222-33/+70
| | | | | | | | | | | As a side effect, the .debug_line section will be dumped in physical order, rather than in the order that compile units refer to their associated portions of the .debug_line section. These are probably always the same order anyway, and no tests noticed the difference. Differential Revision: https://reviews.llvm.org/D39854 llvm-svn: 318839
* [DWARF] Fix handling of extended line-number opcodesPaul Robinson2017-11-221-5/+24
| | | | | | Differential Revision: https://reviews.llvm.org/D40200 llvm-svn: 318838
* AMDGPU: Consider memory dependencies with moved instructions in ↵Nicolai Haehnle2017-11-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SILoadStoreOptimizer Summary: This bug seems to have gone unnoticed because critical cases with LDS instructions are eliminated by the peephole optimizer. However, equivalent situations arise with buffer loads and stores as well, so this fixes regressions since r317751 ("AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4"). Fixes at least: KHR-GL45.shader_storage_buffer_object.basic-operations-case1-cs KHR-GL45.cull_distance.functional piglit tes-input-gl_ClipDistance.shader_test ... and probably more Change-Id: I0e371536288eb8e6afeaa241a185266fd45d129d Reviewers: arsenm, mareko, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D40303 llvm-svn: 318829
* [DAGCombiner] Bugfix in isAlias().Jonas Paulsson2017-11-221-2/+2
| | | | | | | | | | | | | | | | | Since i1 is a legal type, this: NumBytes = Op1->getMemoryVT().getSizeInBits() >> 3; is wrong and should be instead NumBytes = Op0->getMemoryVT().getStoreSize(); There seems to be more places where this should be fixed outside DAGCombiner. Review: Hal Finkel https://bugs.llvm.org/show_bug.cgi?id=35366 llvm-svn: 318824
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