[Hexagon] Remove trailing spaces, NFC

llvm-svn: 318875

2 files changed, 3 insertions, 3 deletions

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index c262bd698c6..c9d1822e8fd 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1151,7 +1151,7 @@ SDValue HexagonTargetLowering::LowerFormalArguments(
       EVT RegVT = VA.getLocVT();
       if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
           RegVT == MVT::i32 || RegVT == MVT::f32) {
-        unsigned VReg = 
+        unsigned VReg =
           RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
         RegInfo.addLiveIn(VA.getLocReg(), VReg);
         SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
index 51ef37f39a7..afd63c69101 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
@@ -63,7 +63,7 @@ let Namespace = "Hexagon" in {
 
   // Rc - control registers
   class Rc<bits<5> num, string n,
-           list<string> alt = [], list<Register> alias = []> : 
+           list<string> alt = [], list<Register> alias = []> :
         HexagonReg<num, n, alt, alias> {
     let Num = num;
   }
@@ -285,7 +285,7 @@ def HvxQR : RegisterClass<"Hexagon", [VecI1], 512, (add Q0, Q1, Q2, Q3)> {
 }
 
 let Size = 32 in
-def PredRegs : RegisterClass<"Hexagon", 
+def PredRegs : RegisterClass<"Hexagon",
   [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>;
 
 let Size = 32 in