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* Make two piece constant generation as a single instruction. It's ↵Evan Cheng2007-03-202-30/+55
| | | | | | re-materialized as a load from constantpool. llvm-svn: 35207
* New entry.Evan Cheng2007-03-201-0/+13
| | | | llvm-svn: 35206
* Added MRegisterInfo hook to re-materialize an instruction.Evan Cheng2007-03-2012-16/+99
| | | | llvm-svn: 35205
* Two changes:Chris Lattner2007-03-202-13/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) codegen a shift of a register as a shift, not an LEA. 2) teach the RA to convert a shift to an LEA instruction if it wants something in three-address form. This gives us asm diffs like: - leal (,%eax,4), %eax + shll $2, %eax which is faster on some processors and smaller on all of them. and, more interestingly: - movl 24(%esi), %eax - leal (,%eax,4), %edi + movl 24(%esi), %edi + shll $2, %edi Without #2, #1 was a significant pessimization in some cases. This implements CodeGen/X86/shift-codegen.ll llvm-svn: 35204
* fix indentationChris Lattner2007-03-201-1/+1
| | | | llvm-svn: 35202
* Regenerate.Reid Spencer2007-03-203-282/+320
| | | | llvm-svn: 35199
* Plug some PATypeHolder memory leaks.Reid Spencer2007-03-201-6/+25
| | | | llvm-svn: 35198
* use types of loads and stores, not address, in CheckForIVReuseDale Johannesen2007-03-201-7/+28
| | | | llvm-svn: 35197
* fix obvious comment bugDale Johannesen2007-03-201-1/+1
| | | | llvm-svn: 35196
* Fix a nasty memory leak, caused by my revamp of the value symbol table.Chris Lattner2007-03-201-0/+5
| | | | llvm-svn: 35195
* Make isOneBitSet faster by using APInt::isPowerOf2. Thanks Chris.Reid Spencer2007-03-201-1/+1
| | | | llvm-svn: 35194
* APIntify the isHighOnes utility function.Reid Spencer2007-03-191-5/+6
| | | | llvm-svn: 35190
* Fix coding standards violation.Reid Spencer2007-03-191-1/+1
| | | | llvm-svn: 35189
* Implement isMaxValueMinusOne in terms of APInt instead of uint64_t.Reid Spencer2007-03-191-5/+4
| | | | | | Patch by Sheng Zhou. llvm-svn: 35188
* Implement isMinValuePlusOne using facilities of APInt instead of uint64_tReid Spencer2007-03-191-5/+4
| | | | | | Patch by Zhou Sheng. llvm-svn: 35187
* Implement isOneBitSet in terms of APInt::countPopulation.Reid Spencer2007-03-191-2/+1
| | | | llvm-svn: 35186
* 1. Use APInt::getSignBit to reduce clutter (patch by Sheng Zhou)Reid Spencer2007-03-191-8/+4
| | | | | | 2. Replace uses of the "isPositive" utility function with APInt::isPositive llvm-svn: 35185
* Remove a redundant clause in an if statement.Reid Spencer2007-03-191-1/+0
| | | | | | Patch by Sheng Zhou. llvm-svn: 35184
* Regenerate.Reid Spencer2007-03-192-156/+146
| | | | llvm-svn: 35183
* Fix test/Assembler/2007-03-19-NegValue.ll by using the new "isSigned"Reid Spencer2007-03-191-9/+4
| | | | | | | parameter on ConstantInt::get to indicate the signedness of the intended value. llvm-svn: 35182
* Allow ConstantInt::get(Ty, uint64_t) to interpret the 64-bit values as aReid Spencer2007-03-191-2/+2
| | | | | | negative number. This is needed to fix test/Assembler/2007-03-19-NegValue.ll llvm-svn: 35181
* Implement extension of sign bits for negative values in the uint64_tReid Spencer2007-03-191-1/+5
| | | | | | constructor. This helps to fix test/Assembler/2007-03-19-NegValue.ll llvm-svn: 35180
* Fix mingw32 buildAnton Korobeynikov2007-03-191-0/+1
| | | | llvm-svn: 35177
* Regenerate.Reid Spencer2007-03-193-579/+607
| | | | llvm-svn: 35174
* For PR1248:Reid Spencer2007-03-191-155/+169
| | | | | | | | | | | Eliminate support for type planes in numbered values. This simplifies the data structures involved in managing forward definitions, etc. Instead of requiring maps from type to value, we can now just use a vector of values. These changes also required rewrites of some support functions such as InsertValue, getBBVal, and ResolveDefinitions. Some other cosmetic changes were made as well. llvm-svn: 35173
* Add and Operator== method to ValID so equality can be done properly forReid Spencer2007-03-191-0/+20
| | | | | | named or numbered ValIDs. llvm-svn: 35172
* For PR1258:Reid Spencer2007-03-191-39/+20
| | | | | | | | | | Radically simplify the SlotMachine. There is no need to keep Value planes around any more. This change causes slot numbering to number all un-named, non-void values starting at 0 and incrementing monotonically through the function, regardless of type (including BasicBlocks). Getting slot numbers is now a single lookup operation instead of a double lookup. llvm-svn: 35171
* fix ScalarRepl/2007-03-19-CanonicalizeMemcpy.llChris Lattner2007-03-191-1/+2
| | | | llvm-svn: 35169
* Remove -reduce-joining-phys-regs options. Make it on by default.Evan Cheng2007-03-191-3/+1
| | | | llvm-svn: 35165
* Fix naming inconsistencies.Evan Cheng2007-03-196-30/+30
| | | | llvm-svn: 35163
* Special LDR instructions to load from non-pc-relative constantpools. These areEvan Cheng2007-03-193-2/+12
| | | | | | rematerializable. Only used for constant generation for now. llvm-svn: 35162
* Constant generation instructions are re-materializable.Evan Cheng2007-03-192-5/+11
| | | | llvm-svn: 35161
* Added isReMaterializable.Evan Cheng2007-03-191-0/+1
| | | | llvm-svn: 35160
* Minor bug fix.Evan Cheng2007-03-191-1/+1
| | | | llvm-svn: 35153
* fix a warningChris Lattner2007-03-191-1/+1
| | | | llvm-svn: 35152
* implement the next chunk of SROA with memset/memcpy's of aggregates. ThisChris Lattner2007-03-191-36/+107
| | | | | | implements Transforms/ScalarRepl/memset-aggregate-byte-leader.ll llvm-svn: 35150
* Clean up this code and fix subtract miscompile.Nick Lewycky2007-03-181-18/+22
| | | | llvm-svn: 35146
* Implement InstCombine/and-xor-merge.ll:test[12].Chris Lattner2007-03-181-54/+96
| | | | | | Rearrange some code to simplify it now that shifts are binops llvm-svn: 35145
* minor updatesChris Lattner2007-03-181-8/+6
| | | | llvm-svn: 35143
* This is implemented. We now generate:Nick Lewycky2007-03-181-40/+0
| | | | | | | | | | | | | | | | | | | | | | entry: icmp ugt i32 %x, 4 ; <i1>:0 [#uses=1] br i1 %0, label %cond_true, label %cond_false cond_true: ; preds = %entry %tmp1 = tail call i32 (...)* @bar( i32 12 ) ; <i32> [#uses=0] ret void cond_false: ; preds = %entry switch i32 %x, label %cond_true15 [ i32 4, label %cond_true3 i32 3, label %cond_true7 i32 2, label %cond_true11 i32 0, label %cond_false17 ] ... llvm-svn: 35142
* - Merge UsedBlocks info after two virtual registers are coalesced.Evan Cheng2007-03-181-23/+30
| | | | | | - Use distance to closest use to determine whether to abort coalescing. llvm-svn: 35141
* Keep UsedBlocks info accurate.Evan Cheng2007-03-182-0/+6
| | | | llvm-svn: 35140
* Propagate ValueRanges across equality.Nick Lewycky2007-03-181-67/+159
| | | | | | Add some more micro-optimizations: x * 0 = 0, a - x = a --> x = 0. llvm-svn: 35138
* Silence warningAnton Korobeynikov2007-03-171-2/+2
| | | | llvm-svn: 35137
* Track the BB's where each virtual register is used.Evan Cheng2007-03-171-15/+22
| | | | llvm-svn: 35135
* Joining a live interval of a physical register with a virtual one can turn outEvan Cheng2007-03-171-0/+54
| | | | | | | | | | | | to be really bad. Once they are joined they are not broken apart. Also, physical intervals cannot be spilled! Added a heuristic as a workaround for this. Be careful coalescing with a physical register if the virtual register uses are "far". Check if there are uses in the same loop as the source (copy instruction). Check if it is in the loop preheader, etc. llvm-svn: 35134
* Use SmallSet instead of std::set.Evan Cheng2007-03-171-1/+1
| | | | llvm-svn: 35133
* If sdisel has decided to sink GEP index expression into any BB. Replace all usesEvan Cheng2007-03-171-22/+37
| | | | | | in that BB. llvm-svn: 35132
* Support 'I' inline asm constraint.Devang Patel2007-03-171-0/+11
| | | | llvm-svn: 35129
* Only ARMv6 has BSWAP.Lauro Ramos Venancio2007-03-161-0/+4
| | | | | | Fix MultiSource/Applications/aha test. llvm-svn: 35128
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