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authorEvan Cheng <evan.cheng@apple.com>2007-03-19 06:22:07 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-03-19 06:22:07 +0000
commit461c964d3d707a8b14fb6f53c0c39597b1511c4b (patch)
tree6d0d1567ef34cd773547e652b0d41a03d5c01321 /llvm/lib
parent9d7d130835382a9f7b39def3a3bbcbb6b2a611ce (diff)
downloadbcm5719-llvm-461c964d3d707a8b14fb6f53c0c39597b1511c4b.tar.gz
bcm5719-llvm-461c964d3d707a8b14fb6f53c0c39597b1511c4b.zip
Added isReMaterializable.
llvm-svn: 35160
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Target.td1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/Target.td b/llvm/lib/Target/Target.td
index fbc972a2928..b1ef5c93579 100644
--- a/llvm/lib/Target/Target.td
+++ b/llvm/lib/Target/Target.td
@@ -165,6 +165,7 @@ class Instruction {
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?
bit isTerminator = 0; // Is this part of the terminator for a basic block?
+ bit isReMaterializable = 0; // Is this instruction re-materializable?
bit hasDelaySlot = 0; // Does this instruction have an delay slot?
bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
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