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| author | Evan Cheng <evan.cheng@apple.com> | 2007-03-19 07:20:03 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-03-19 07:20:03 +0000 |
| commit | ee2763f76f905b899460459e3e9730a8a854aff5 (patch) | |
| tree | d3effd13f6e60bf64dc41b8e262240d343802a2d /llvm/lib | |
| parent | 5be3e09a3052490d9b1f38a54f9e962a58024798 (diff) | |
| download | bcm5719-llvm-ee2763f76f905b899460459e3e9730a8a854aff5.tar.gz bcm5719-llvm-ee2763f76f905b899460459e3e9730a8a854aff5.zip | |
Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for constant generation for now.
llvm-svn: 35162
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb.td | 5 |
3 files changed, 12 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index b0c040b39d7..7c40a712212 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -551,7 +551,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { SDNode *ResNode; if (Subtarget->isThumb()) - ResNode = CurDAG->getTargetNode(ARM::tLDRpci, MVT::i32, MVT::Other, + ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other, CPIdx, CurDAG->getEntryNode()); else { SDOperand Ops[] = { @@ -560,7 +560,7 @@ SDNode *ARMDAGToDAGISel::Select(SDOperand Op) { CurDAG->getTargetConstant(0, MVT::i32), CurDAG->getEntryNode() }; - ResNode = CurDAG->getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4); + ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 4); } ReplaceUses(Op, SDOperand(ResNode, 0)); return NULL; diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index cb0a508bf93..b222c5b0ee9 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -580,6 +580,11 @@ def LDR : AI2<(ops GPR:$dst, addrmode2:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load addrmode2:$addr))]>; +// Special LDR for loads from non-pc-relative constpools. +let isReMaterializable = 1 in +def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr), + "ldr $dst, $addr", []>; + // Loads with zero extension def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr), "ldrh $dst, $addr", diff --git a/llvm/lib/Target/ARM/ARMInstrThumb.td b/llvm/lib/Target/ARM/ARMInstrThumb.td index 6b289d9a051..a70bf96fd02 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb.td @@ -248,6 +248,11 @@ def tRestore : TIs<(ops GPR:$dst, t_addrmode_sp:$addr), def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr), "ldr $dst, $addr", [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>; + +// Special LDR for loads from non-pc-relative constpools. +let isReMaterializable = 1 in +def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr), + "ldr $dst, $addr", []>; } // isLoad let isStore = 1 in { |
