summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
...
* llvm-undname: Fix an assert-on-invalidNico Weber2019-04-031-0/+5
| | | | | | | | Found by oss-fuzz, fixes issues 12428 and 12429 on oss-fuzz. Differential Revision: https://reviews.llvm.org/D60204 llvm-svn: 357647
* llvm-undname: Fix a crash-on-invalidNico Weber2019-04-031-0/+4
| | | | | | | | Found by oss-fuzz, fixes issues 12435 and 12438 on oss-fuzz. Differential Revision: https://reviews.llvm.org/D60202 llvm-svn: 357646
* [x86] fold shuffles of h-ops that have an undef operandSanjay Patel2019-04-031-2/+2
| | | | | | | If an operand is undef, we can assume it's the same as the other operand. llvm-svn: 357644
* [x86] eliminate movddup of horizontal opSanjay Patel2019-04-031-2/+11
| | | | | | | | | | | | This pattern would show up as a regression if we more aggressively convert vector FP ops to scalar ops. There's still a missed optimization for the v4f64 legal case (AVX) because we create that h-op with an undef operand. We should probably just duplicate the operands for that pattern to avoid trouble. llvm-svn: 357642
* [IR] Create new method in `Function` class (NFC)Evandro Menezes2019-04-0316-25/+21
| | | | | | | | | Create method `optForNone()` testing for the function level equivalent of `-O0` and refactor appropriately. Differential revision: https://reviews.llvm.org/D59852 llvm-svn: 357638
* AMDGPU: Split block for si_end_cfMatt Arsenault2019-04-035-17/+128
| | | | | | | | | | | | | | | Relying on no spill or other code being inserted before this was precarious. It relied on code diligently checking isBasicBlockPrologue which is likely to be forgotten. Ideally this could be done earlier, but this doesn't work because of phis. Any other instruction can't be placed before them, so we have to accept the position being incorrect during SSA. This avoids regressions in the fast register allocator rewrite from inverting the direction. llvm-svn: 357634
* [dwarfdump] Remove bogus verifier errorJonas Devlieghere2019-04-031-11/+1
| | | | | | | | The standard doesn't require a DW_TAG_variable, DW_TAG_formal_parameter or DW_TAG_constant to A DW_AT_type attribute describing the type of the variable. It only specifies that it *can* have one. llvm-svn: 357628
* [ProfileSummary] Count callsite samples when computing total samples.Taewook Oh2019-04-031-4/+9
| | | | | | | | | | | | | | Summary: Currently ProfileSummaryBuilder doesn't count into callsite samples when computing total samples. Considering that ProfileSummaryInfo is used to checked the hotness of not only body samples but also callsite samples (from SampleProfileLoader), I think the callsite sample counts should be considered when computing total samples. Reviewers: eraman, danielcdh, wmi Subscribers: hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59835 llvm-svn: 357627
* [X86] Extend boolean arguments to inline-asm according to getBooleanTypeKrzysztof Parzyszek2019-04-031-2/+7
| | | | | | Differential Revision: https://reviews.llvm.org/D60208 llvm-svn: 357615
* [X86][AVX] combineHorizontalPredicateResult - split any/allof v16i16/v32i8 ↵Simon Pilgrim2019-04-031-1/+8
| | | | | | | | reduction on AVX1 Perform the 2 x 128-bit lo/hi OR/AND on the vectors before calling PMOVMSKB on the 128-bit result. llvm-svn: 357611
* [X86][AVX] combineHorizontalPredicateResult - support v16i16/v32i8 reduction ↵Simon Pilgrim2019-04-031-6/+3
| | | | | | | | on AVX1 Use getPMOVMSKB helper which splits v32i8 MOVMSK calls on pre-AVX2 targets. llvm-svn: 357608
* [DWARF] check whether the DIE is valid before querying for informationPaul Semel2019-04-031-0/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D60147 llvm-svn: 357607
* [AArch64][GlobalISel] Legalize G_FEXP2Jessica Paquette2019-04-032-2/+7
| | | | | | | | | Same as G_EXP. Add a test, and update legalizer-info-validation.mir and f16-instructions.ll. Differential Revision: https://reviews.llvm.org/D60165 llvm-svn: 357605
* [DAGCombiner] Rename variables Demanded -> DemandedBits/DemandedElts. NFCI.Simon Pilgrim2019-04-031-9/+10
| | | | | | Use consistent variable names down the SimplifyDemanded* call stack so debugging isn't such a annoyance. llvm-svn: 357602
* Test commit: Remove double variable assignmentLewis Revill2019-04-031-1/+1
| | | | llvm-svn: 357601
* [SystemZ] Improve codegen for certain SADDO-immediate casesUlrich Weigand2019-04-032-0/+28
| | | | | | | | | | | | When performing an add-with-overflow with an immediate in the range -2G ... -4G, code currently loads the immediate into a register, which generally takes two instructions. In this particular case, it is preferable to load the negated immediate into a register instead, which always only requires one instruction, and then perform a subtract. llvm-svn: 357597
* [yaml2obj][obj2yaml] - Change how symbol's binding is descibed when ↵George Rimar2019-04-031-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | parsing/dumping. Currently, YAML has the following syntax for describing the symbols: Symbols: Local: LocalSymbol1: ... LocalSymbol2: ... ... Global: GlobalSymbol1: ... Weak: ... GNUUnique: I.e. symbols are grouped by their bindings. That is not very convenient, because: It does not allow to set a custom binding, what can be useful for producing broken/special outputs for test cases. Adding a new binding would require to change a syntax (what we observed when added GNUUnique recently). It does not allow to change the order of the symbols in .symtab/.dynsym, i.e. currently all Local symbols are placed first, then Global, Weak and GNUUnique are following, but we are not able to change the order. It is not consistent. Binding is just one of the properties of the symbol, we do not group them by other properties. It makes the code more complex that it can be. This patch shows it can be simplified with the change performed. The patch changes the syntax to just: Symbols: Symbol1: ... Symbol2: ... ... With that, we are able to work with the binding field just like with any other symbol property. Differential revision: https://reviews.llvm.org/D60122 llvm-svn: 357595
* [MIPS GlobalISel] Select floating point arithmetic operationsPetar Avramovic2019-04-032-5/+20
| | | | | | | | Select 32 and 64 bit floating point add, sub, mul and div for MIPS32. Differential Revision: https://reviews.llvm.org/D60191 llvm-svn: 357584
* [AArch64] Update v8.5a MTE LDG/STG instructionsJaved Absar2019-04-031-12/+12
| | | | | | | | | | | | | The latest MTE specification adds register Xt to the STG instruction family: STG [Xn, #offset] -> STG Xt, [Xn, #offset] The tag written to memory is taken from Xt rather than Xn. Also, the LDG instruction also was changed to read return address from Xt: LDG Xt, [Xn, #offset]. This patch includes those changes and tests. Specification is at: https://developer.arm.com/docs/ddi0596/c Differential Revision: https://reviews.llvm.org/D60188 llvm-svn: 357583
* [DAGCombiner] loosen restrictions for moving shuffles after vector binopSanjay Patel2019-04-031-16/+19
| | | | | | | | | | | | There are 3 changes to make this correspond to the same transform in instcombine: 1. Remove the legality check - we can't create anything less legal than we started with. 2. Ease the use restriction, so we only bail out if both operands have >1 use. 3. Ease the use restriction for binops with a repeated operand (eg, mul x, x). As discussed in D60150, there's a scalarization opportunity that will be made easier by allowing this transform more generally. llvm-svn: 357580
* [DAGCombine] Don't use getZExtValue() until we know the constant is in range.Simon Pilgrim2019-04-031-2/+2
| | | | | | Noticed during prep for a patch for PR40758. llvm-svn: 357571
* [mips] Remove unused FGRH32 register class. NFCSimon Atanasyan2019-04-032-32/+0
| | | | | | | | If we need this class in the future we will easily restore it. Differential Revision: http://reviews.llvm.org/D60132 llvm-svn: 357570
* [X86] Make the post machine scheduler macrofusion-aware.Clement Courbet2019-04-031-0/+7
| | | | | | | | | | | | | | | | Summary: Given that X86 does not use this currently, this is an NFC. I'll experiment with enabling and will report numbers. Reviewers: andreadb, lebedev.ri Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60185 llvm-svn: 357568
* [InstCombine] Simplify ctpop with bitreverse/bswapDavid Bolvansky2019-04-031-0/+8
| | | | | | | | | | | | | | | | Summary: Fixes PR41337 Reviewers: spatel Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60148 llvm-svn: 357564
* Revert r357256 "[DAGCombine] Improve Lifetime node chains."Hans Wennborg2019-04-031-31/+0
| | | | | | | | | | | | | | | | | | | | | | | | As it caused a pathological compile-time regressionin V8, see PR41352. > Improve both start and end lifetime nodes chain dependencies. > > Reviewers: courbet > > Reviewed By: courbet > > Subscribers: hiraditya, llvm-commits > > Tags: #llvm > > Differential Revision: https://reviews.llvm.org/D59795 This also reverts the follow-up r357309: > [DAGCombiner] Rewrite ImproveLifetimeNodeChain to avoid DAG loop. > > Avoid EXPENSIVE_CHECK failure. NFCI. llvm-svn: 357563
* AMDGPU: Assume ECC is enabled by default if supportedMatt Arsenault2019-04-034-6/+32
| | | | | | | | | | The test should really be checking for the property directly in the code object headers, but there are problems with this. I don't see this directly represented in the text form, and for the binary emission this is depending on a function level subtarget feature to emit a global flag. llvm-svn: 357558
* [WebAssembly] Add Emscripten OS definition + small_printfAlon Zakai2019-04-033-2/+63
| | | | | | | | | | | | | | | The Emscripten OS provides a definition of __EMSCRIPTEN__, and also that it supports iprintf optimizations. Also define small_printf optimizations, which is a printf with float support but not long double (which in wasm can be useful since long doubles are 128 bit and force linking of float128 emulation code). This part is based on sunfish's https://reviews.llvm.org/D57620 (which can't land yet since the WASI integration isn't ready yet). Differential Revision: https://reviews.llvm.org/D60167 llvm-svn: 357552
* InstSimplify: Fold round intrinsics from sitofp/uitofpMatt Arsenault2019-04-031-0/+16
| | | | | | https://godbolt.org/z/gEMRZb llvm-svn: 357549
* [WebAssembly] Remove unneeded target operand flagsSam Clegg2019-04-037-50/+32
| | | | | | | | | | | This change is in preparation for the addition of new target operand flags for new relocation types. Have a symbol type as part of the flag set makes it harder to use and AFAICT these are serving no purpose. Differential Revision: https://reviews.llvm.org/D60014 llvm-svn: 357548
* AMDGPU: Remove unnecessary subtarget getMatt Arsenault2019-04-031-1/+0
| | | | llvm-svn: 357542
* AMDGPU: Fix names for generation featuresMatt Arsenault2019-04-034-10/+17
| | | | | | | | We should overall stop using these, but the uppercase name didn't work. Any feature string is converted to lowercase, so these could never be found in the table. llvm-svn: 357541
* [GlobalISel] Add IRTranslator support for llvm.stacksave and llvm.stackrestoreJessica Paquette2019-04-021-0/+28
| | | | | | | | Also update arm64-irtranslator.ll. Differential Revision: https://reviews.llvm.org/D60140 llvm-svn: 357538
* [X86] Mark the default case of the X86InstrInfo::convertToThreeAddress ↵Craig Topper2019-04-021-1/+1
| | | | | | | | | switch as unreachable. This function should only be called with instructions that are really convertible. And all convertible instructions need to be handled by the switch. So nothing should use the default. llvm-svn: 357529
* [X86] Check MI.isConvertibleTo3Addr() before calling convertToThreeAddress ↵Craig Topper2019-04-021-0/+6
| | | | | | | | | | in X86FixupLEAs. X86FixupLEAs just assumes convertToThreeAddress will return nullptr for any instruction that isn't convertible. But the code in convertToThreeAddress for X86 assumes that any instruction coming in has at least 2 operands and that the second one is a register. But those properties aren't guaranteed of all instructions. We should check the instruction property first. llvm-svn: 357528
* [InstCombine] Simplify ctlz/cttz with bitreverseDavid Bolvansky2019-04-021-1/+9
| | | | | | | | | | | | | | | | Summary: Fixes PR41273 Reviewers: spatel Reviewed By: spatel Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60096 llvm-svn: 357521
* [AArch64][GlobalISel] Select llvm.aarch64.stlxr(i64, i64*)Jessica Paquette2019-04-021-8/+68
| | | | | | | | | | | | | This adds partial instruction selection support for llvm.aarch64.stlxr. It also factors out selection for G_INTRINSIC_W_SIDE_EFFECTS into its own function. The new function removes the restriction that the intrinsic ID on the G_INTRINSIC_W_SIDE_EFFECTS be on operand 0. Also add a test, and add a GISel line to arm64-ldxr-stxr.ll. Differential Revision: https://reviews.llvm.org/D60100 llvm-svn: 357518
* [ArgPromotion] Set debug location at updated callsitesVedant Kumar2019-04-021-7/+9
| | | | | | | | | | | | Set the correct debug location on instructions which load arguments in preparation for a call to an arg-promoted function. This prevents location cascade from misattributing the line/scope of one of these loads to the location of the instruction preceding the call. Differential Revision: https://reviews.llvm.org/D60113 llvm-svn: 357500
* [DebugInfo] Fix pr41180 : Loop Vectorization Debugify FailureVedant Kumar2019-04-021-3/+21
| | | | | | | | | | | | | | | | | | | | | Bug: https://bugs.llvm.org/show_bug.cgi?id=41180 In the bug test case the debug location was missing for the cmp instruction in the "middle block" BB. This patch fixes the bug by copying the debug location from the cmp of the scalar loop's terminator branch, if it exists. The patch also fixes the debug location on the subsequent branch instruction. It was previously using the location of the of the original loop's pre-header block terminator. Both of these instructions will now map to the source line of the conditional branch in the original loop. A regression test has been added that covers these issues. Patch by Orlando Cazalet-Hyams! Differential Revision: https://reviews.llvm.org/D59944 llvm-svn: 357499
* [DAGCombiner] reduce code duplication; NFCSanjay Patel2019-04-021-8/+8
| | | | llvm-svn: 357498
* [X86] Allow FixupLEAs to form INC/DEC under OptSize not just MinSizeCraig Topper2019-04-021-1/+1
| | | | | | This matches our usual INC/DEC heuristic used during isel. llvm-svn: 357497
* [PowerPC] Fix reversed bit issue in DCMX mask for "xvtstdcdp" and ↵Stefan Pintilie2019-04-021-2/+2
| | | | | | | | | | | | | | | | "xvtstdcsp" P9 implementation Did experiments on power 9 machine, checked the outputs for NaN & Infinity+ cases with corresponding DCMX bit set. Confirmed the DCMX mask bit for NaN and infinity+ are reversed. This patch fixes the issue. Patch by Victor Huang. Differential Revision: https://reviews.llvm.org/D59384 llvm-svn: 357494
* [WideableCond] Fix a nasty bug in detection of "explicit guards"Philip Reames2019-04-021-2/+7
| | | | | | | | The code was failing to actually check for the presence of the call to widenable_condition. The whole point of specifying the widenable_condition intrinsic was allowing widening transforms. A normal branch is not widenable. A normal branch leading to a deopt is not widenable (in general). I added a test case via LoopPredication, but GuardWidening has an analogous bug. Those are the only two passes actually using this utility just yet. Noticed while working on LoopPredication for non-widenable branches; POC in D60111. llvm-svn: 357493
* [SLP] reorderInputsAccordingToOpcode is const method. NFCI.Simon Pilgrim2019-04-021-5/+4
| | | | llvm-svn: 357490
* [BPF] Replace fstream and sstream with line_iteratorFangrui Song2019-04-021-11/+10
| | | | | | | | | | | | | | | | Summary: This makes libLLVMBPFCodeGen.so 1128 bytes smaller for my build. Reviewers: yonghong-song Reviewed By: yonghong-song Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60117 llvm-svn: 357489
* [SimplifyCFG] Don't split musttail call from retJoseph Tremoulet2019-04-021-1/+1
| | | | | | | | | | | | | | | | | | | Summary: When inserting an `unreachable` after a noreturn call, we must ensure that it's not a musttail call to avoid breaking the IR invariants for musttail calls. Reviewers: fedor.sergeev, majnemer Reviewed By: majnemer Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60080 llvm-svn: 357485
* [SampleProfile] Repeat indirect call promotion only when the target is ↵Taewook Oh2019-04-021-0/+3
| | | | | | | | | | | | | | | | actually hot. Summary: It is possible that multiple indirect call targets have been promoted for a single callsite from the profiled binary. Current implementation repeats promotion for all these targets as far as the callsite itself is hot (the callsite is assumed to be hot if any one of these targets was "hot" during the profiling). However, even when one of the ICPed target is hot other targets may not, and we should not repeat promotion for "cold" targets. Reviewers: danielcdh, wmi Subscribers: hiraditya, jdoerfert, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59940 llvm-svn: 357484
* [PruneEH] Don't split musttail call from retJoseph Tremoulet2019-04-021-1/+2
| | | | | | | | | | | | | | | | | | | Summary: When inserting an `unreachable` after a noreturn call, we must ensure that it's not a musttail call to avoid breaking the IR invariants for musttail calls. Reviewers: fedor.sergeev, majnemer Reviewed By: majnemer Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60079 llvm-svn: 357483
* [SystemZ] Improve instruction selection of 64 bit shifts and rotates.Jonas Paulsson2019-04-022-0/+20
| | | | | | | | | | | | | | | | For shift and rotate instructions that only use the last 6 bits of the shift amount, a shift amount of (x*64-s) can be substituted with (-s). This saves one instruction and a register: lhi %r1, 64 sr %r1, %r3 sllg %r2, %r2, 0(%r1) => lcr %r1, %r3 sllg %r2, %r2, 0(%r1) Review: Ulrich Weigand llvm-svn: 357481
* [Transforms] Redundant getValueOperand (NFC)Brian Gesiak2019-04-021-2/+2
| | | | | | | | | `StoreInst::getValueOperand` is identical to `getOperand(0)`, so the call to `getOperand(0)` can be replaced. Further, `SI->getValueOperand` is redundantly called just a few lines down, despite its return value being stored in variable `DV`. No functional change. llvm-svn: 357479
* [mips] Remove the override of the `isMachineVerifierClean()`Simon Atanasyan2019-04-021-4/+0
| | | | | | All issues found by machine verifier in MIPS target have been fixed. llvm-svn: 357473
OpenPOWER on IntegriCloud