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* Strip trailing whitespace. NFCI.Simon Pilgrim2016-02-271-9/+9
| | | | llvm-svn: 262131
* [PM] Provide explicit instantiation declarations and definitions for theChandler Carruth2016-02-273-0/+8
| | | | | | PassManager and AnalysisManager template specializations as well. llvm-svn: 262128
* [PM] Provide two templates for the two directionalities of analysisChandler Carruth2016-02-273-109/+16
| | | | | | | | | | | | | | | | | | | | | | | | manager proxies and use those rather than repeating their definition four times. There are real differences between the two directions: outer AMs are const and don't need to have invalidation tracked. But every proxy in a particular direction is identical except for the analysis manager type and the IR unit they proxy into. This makes them prime candidates for nice templates. I've started introducing explicit template instantiation declarations and definitions as well because we really shouldn't be emitting all this everywhere. I'm going to go back and add the same for the other templates like this in a follow-up patch. I've left the analysis manager as an opaque type rather than using two IR units and requiring it to be an AnalysisManager template specialization. I think its important that users retain the ability to provide their own custom analysis management layer and provided it has the appropriate API everything should Just Work. llvm-svn: 262127
* DAGCombiner: Relax sqrt NaN folding checkMatt Arsenault2016-02-271-7/+7
| | | | | | This is OK for +0 since compares to +/-0 give the same result. llvm-svn: 262125
* AMDGPU: Split vi-insts subtarget featureMatt Arsenault2016-02-273-6/+24
| | | | | | | This will be more useful for marking builtins acceptable for which subtargets. llvm-svn: 262121
* AMDGPU: Add s_sleep intrinsicMatt Arsenault2016-02-272-1/+17
| | | | llvm-svn: 262120
* AMDGPU: Implement readcyclecounterMatt Arsenault2016-02-277-10/+68
| | | | | | | | | | This matches the behavior of the HSAIL clock instruction. s_realmemtime is used if the subtarget supports it, and falls back to s_memtime if not. Also introduces new intrinsics for each of s_memtime / s_memrealtime. llvm-svn: 262119
* CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFCDuncan P. N. Exon Smith2016-02-2723-186/+184
| | | | | | | | | | | | | | Take MachineInstr by reference instead of by pointer in SlotIndexes and the SlotIndex wrappers in LiveIntervals. The MachineInstrs here are never null, so this cleans up the API a bit. It also incidentally removes a few implicit conversions from MachineInstrBundleIterator to MachineInstr* (see PR26753). At a couple of call sites it was convenient to convert to a range-based for loop over MachineBasicBlock::instr_begin/instr_end, so I added MachineBasicBlock::instrs. llvm-svn: 262115
* [instrprof] Use __{start,stop}_SECNAME on PS4 too.Sean Silva2016-02-271-1/+2
| | | | | | | | | | | | | | | | | | | | | Summary: The PS4 linker seems to handle this fine. Hi David, it seems that indeed most ELF linkers support __{start,stop}_SECNAME, as our proprietary linker does as well. This follows the pattern of r250679 w.r.t. the testing. Maggie, Phillip, Paul: I've tested this with the PS4 SDK 3.5 toolchain prerelease and it seems to work fine. Reviewers: davidxl Subscribers: probinson, phillip.power, MaggieYi Differential Revision: http://reviews.llvm.org/D17672 llvm-svn: 262112
* [sancov] properly initializing pass.Mike Aizatsky2016-02-271-1/+6
| | | | llvm-svn: 262111
* [libFuzzer] don't emit callbacks to sanitizer run-time in ↵Kostya Serebryany2016-02-271-12/+14
| | | | | | -fsanitize-coverage=trace-pc mode; update libFuzzer doc for previous commit llvm-svn: 262110
* Suppress an uncovered switch warning [NFC]Philip Reames2016-02-271-0/+1
| | | | llvm-svn: 262109
* [LICM] Teach LICM how to handle cases where the alias set tracker wasChandler Carruth2016-02-271-20/+32
| | | | | | | | | | | | | | | | | | | | merged into a loop that was subsequently unrolled (or otherwise nuked). In this case it can't merge in the ASTs for any remaining nested loops, it needs to re-add their instructions dircetly. The fix is very isolated, but I've pulled the code for merging blocks into the AST into a single place in the process. The only behavior change is in the case which would have crashed before. This fixes a crash reported by Mikael Holmen on the list after r261316 restored much of the loop pass pipelining and allowed us to actually do this kind of nested transformation sequenc. I've taken that test case and further reduced it into the somewhat twisty maze of loops in the included test case. This does in fact trigger the bug even in this reduced form. llvm-svn: 262108
* [libFuzzer] fixing the botKostya Serebryany2016-02-271-1/+1
| | | | llvm-svn: 262106
* [sancov] do not instrument nodes that are full pre-dominatorsMike Aizatsky2016-02-271-11/+22
| | | | | | | | | | | Summary: Without tree pruning clang has 2,667,552 points. Wiht only dominators pruning: 1,515,586. With both dominators & predominators pruning: 1,340,534. Differential Revision: http://reviews.llvm.org/D17671 llvm-svn: 262103
* [libFuzzer] speedup path coverage handlingKostya Serebryany2016-02-272-18/+19
| | | | llvm-svn: 262102
* Minor code cleanup. NFC.Junmo Park2016-02-271-1/+1
| | | | llvm-svn: 262096
* [InstCombine] Be more conservative about removing stackrestoreReid Kleckner2016-02-271-1/+7
| | | | | | | We ended up removing a save/restore pair around an inalloca call, leading to a miscompile in Chromium. llvm-svn: 262095
* Fix a bug in isVectorReductionOp() in SelectionDAGBuilder.cpp that may cause ↵Cong Hou2016-02-261-4/+4
| | | | | | assertion failure on AArch64. llvm-svn: 262091
* [X86] Fix a stale comment. NFC.Ahmed Bougacha2016-02-261-2/+2
| | | | llvm-svn: 262087
* [X86] Remove the unused SDTX86atomicBinary. NFC.Ahmed Bougacha2016-02-261-2/+0
| | | | llvm-svn: 262086
* [LVI] Extend select handling to catch min/max/clamp idiomsPhilip Reames2016-02-261-3/+71
| | | | | | | | | | Most of this is fairly straight forward. Add handling for min/max via existing matcher utility and ConstantRange routines. Add handling for clamp by exploiting condition constraints on inputs. Note that I'm only handling two constant ranges at this point. It would be reasonable to consider treating overdefined as a full range if the instruction is typed as an integer, but that should be a separate change. Differential Revision: http://reviews.llvm.org/D17184 llvm-svn: 262085
* [libFuzzer] add -print_final_stats=1 flagKostya Serebryany2016-02-266-3/+41
| | | | llvm-svn: 262084
* Strip trailing whitespace. NFCI.Simon Pilgrim2016-02-262-10/+10
| | | | llvm-svn: 262083
* [ConstantRange] Add umin/smin operatorsPhilip Reames2016-02-261-0/+26
| | | | | | | | This was split off from http://reviews.llvm.org/D17184. Reviewed by: Sanjoy llvm-svn: 262080
* [PPC] Legalize FNEG on PPC when possibleKit Barton2016-02-261-0/+3
| | | | | | | | Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has native support for this opcode Phabricator: http://reviews.llvm.org/D17647 llvm-svn: 262079
* Fix spelling. NFCI.Simon Pilgrim2016-02-261-1/+1
| | | | llvm-svn: 262078
* [x86, InstCombine] transform x86 AVX2 masked stores to LLVM intrinsicsSanjay Patel2016-02-261-1/+4
| | | | | | | | | Replicate everything for integers...because x86. Continuation of: http://reviews.llvm.org/rL262064 llvm-svn: 262077
* [libFuzzer] initial implementation of path coverage based on ↵Kostya Serebryany2016-02-267-0/+103
| | | | | | -fsanitize-coverage=trace-pc. This does not scale well yet, but already cracks FullCoverageSetTest in seconds llvm-svn: 262073
* Power9] Implement new vsx instructions: compare and conversionKit Barton2016-02-266-0/+257
| | | | | | | | | | | | | | | | | | | This change implements the following vsx instructions: Quad/Double-Precision Compare: xscmpoqp xscmpuqp xscmpexpdp xscmpexpqp xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp xvcmpnedp(.) xvcmpnesp(.) Quad-Precision Floating-Point Conversion xscvqpdp(o) xscvdpqp xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz xscvsdqp xscvudqp xscvdphp xscvhpdp xvcvhpsp xvcvsphp xsrqpi xsrqpix xsrqpxp 28 instructions Phabricator: http://reviews.llvm.org/D16709 llvm-svn: 262068
* [x86, InstCombine] transform x86 AVX masked stores to LLVM intrinsicsSanjay Patel2016-02-261-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The intended effect of this patch in conjunction with: http://reviews.llvm.org/rL259392 http://reviews.llvm.org/rL260145 is that customers using the AVX intrinsics in C will benefit from combines when the store mask is constant: void mstore_zero_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set1_epi32(0), v); } void mstore_fake_ones_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set1_epi32(1), v); } void mstore_ones_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set1_epi32(0x80000000), v); } void mstore_one_set_elt_mask(float *f, __m128 v) { _mm_maskstore_ps(f, _mm_set_epi32(0x80000000, 0, 0, 0), v); } ...so none of the above will actually generate a masked store for optimized code. Differential Revision: http://reviews.llvm.org/D17485 llvm-svn: 262064
* [x86] refactor to eliminate duplicated code; NFCISanjay Patel2016-02-261-23/+12
| | | | llvm-svn: 262062
* Fix warning in DwarfCFIException. NFCAmaury Sechet2016-02-261-1/+1
| | | | llvm-svn: 262061
* Extract the method to begin and end a fragment in AsmPrinterHandler in their ↵Amaury Sechet2016-02-264-12/+43
| | | | | | | | | | | | | | own method. NFC Summary: This is extracted from D17555 Reviewers: davidxl, reames, sanjoy, MatzeB, pete Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D17580 llvm-svn: 262058
* [GlobalISel] Fix a ranlib warning about empty TOC.Quentin Colombet2016-02-261-3/+6
| | | | | | Fixes PR26733 llvm-svn: 262057
* Fix Sparc 32bit Lowering to rebundle up v2i32 values.Nirav Dave2016-02-261-4/+23
| | | | | | | | | | | | Summary: Fix LowerCall to rebundle v2i32 values after lowering and add testcase Reviewers: jyknight Subscribers: llvm-commits, jyknight Differential Revision: http://reviews.llvm.org/D17615 llvm-svn: 262048
* [x86, AVX] fold 'isPositive' 256-bit vector integer operations (PR26701)Sanjay Patel2016-02-261-4/+13
| | | | | | | This extends the fold introduced with: http://reviews.llvm.org/rL262036 llvm-svn: 262047
* [IR] Optimize bitfield layout of Value for MSVCReid Kleckner2016-02-261-0/+2
| | | | | | | | | | | | | | | This should save a pointer of padding from all MSVC Value subclasses. Recall that MSVC will not pack the following bitfields together: unsigned Bits : 29; unsigned Flag1 : 1; unsigned Flag2 : 1; unsigned Flag3 : 1; Add a static_assert because LLVM developers always trip over this behavior. This regressed in June. llvm-svn: 262045
* [CMAKE] Update build on recent HaikuRenato Golin2016-02-261-1/+3
| | | | | | | | | This patch updates cmake build scripts to build on Haiku. It adds Haiku x86_64 to config.guess. Please consider reviewing. Pathc by Jérôme Duval. llvm-svn: 262038
* [x86, SSE] fold 'isPositive' vector integer operations (PR26701)Sanjay Patel2016-02-261-0/+42
| | | | | | | | | | | | | This is one of the cases shown in: https://llvm.org/bugs/show_bug.cgi?id=26701 Shift and negate is what InstCombine appears to prefer, so I've started with that pattern. Note that the 'pcmpeq' instructions are always generating the negative one for the actual 'pcmpgt' comparison in each case (side note: why isn't there an alias mnemonic for that?). Differential Revision: http://reviews.llvm.org/D17630 llvm-svn: 262036
* [WinEH] Fix funclet return block clobber mask placementReid Kleckner2016-02-261-2/+6
| | | | | | | | | | | | | | | | | | MBB slot index intervals are half open, not closed. getMBBEndIndex() returns the slot index of the start of the next block in layout order. Placing a register mask there is incorrect if the successor of the funclet return is not laid out after the return. Clang generates IR for catch bodies before generating the following normal code, so we never noticed this issue until the D frontend authors filed a bug about it. Instead, we can put the clobber mask on the last instruction of the funclet return block. We still aren't using a register mask operand on the CATCHRET instruction because it would cause PEI to spill all CSRs, including XMM regs, in the prologue. Fixes PR26679. llvm-svn: 262035
* [PM] Finish removing references to fix MSVC builds. Somehow adding baseChandler Carruth2016-02-261-8/+16
| | | | | | | | | classes changed whether the decltype of these expressions was a reference. I'm somewhat horrified why, and there may need to be a deeper fix on MSVC, but this should at least get the bots a step further. llvm-svn: 262008
* Reverting breaking change. Sorry.Chris Dewhurst2016-02-264-303/+10
| | | | llvm-svn: 262007
* [PM] Speculative patch to try and fix MSVC's compilation.Chandler Carruth2016-02-261-1/+3
| | | | | | No idea why r262004 triggered this, but just trying to fix somehow. llvm-svn: 262006
* Reviewed at reviews.llvm.org/D17133Chris Dewhurst2016-02-264-10/+303
| | | | llvm-svn: 262005
* [PM] Introduce CRTP mixin base classes to help define passes andChandler Carruth2016-02-2623-79/+4
| | | | | | | | | | | | | | | | | analyses in the new pass manager. These just handle really basic stuff: turning a type name into a string statically that is nice to print in logs, and getting a static unique ID for each analysis. Sadly, the format of passes in anonymous namespaces makes using their names in tests really annoying so I've customized the names of the no-op passes to keep tests sane to read. This is the first of a few simplifying refactorings for the new pass manager that should reduce boilerplate and confusion. llvm-svn: 262004
* Initial test commit onlyChris Dewhurst2016-02-261-1/+0
| | | | llvm-svn: 262003
* [AMDGPU] Assembler: Basic support for MIMGNikolay Haustov2016-02-266-59/+202
| | | | | | | | | | | Add parsing and printing of image operands. Matches legacy sp3 assembler. Change image instruction order to have data/image/sampler operands in the beginning. This is needed because optional operands in MC are always last. Update SITargetLowering for new order. Add basic MC test. Update CodeGen tests. Review: http://reviews.llvm.org/D17574 llvm-svn: 261995
* [AArch64] Slight cleanup in FPLoadBalancingJames Molloy2016-02-261-2/+1
| | | | | | | | Instead of the convoluted if-statment we can just use getColor. This also fixes a bug where we relied upon the parity of tablegen-generated register indexes (instead of using the machine encoding). llvm-svn: 261990
* [X86] Null out some redundant patterns for masked vector register to ↵Craig Topper2016-02-261-10/+19
| | | | | | | | register moves. These can be accomplished with both aligned and unaligned opcodes. Currently aligned is what is being used so remove the redundant patterns for the unaligned versions. But don't do this for the byte and word vector types since they don't have aligned versions. llvm-svn: 261985
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