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| author | Kit Barton <kbarton@ca.ibm.com> | 2016-02-26 21:59:44 +0000 |
|---|---|---|
| committer | Kit Barton <kbarton@ca.ibm.com> | 2016-02-26 21:59:44 +0000 |
| commit | 915c5ecee16658544c5a35eabd7cbc404cdedd0d (patch) | |
| tree | 916a80108da5acfbf100f45788d11c806a783c7b /llvm/lib | |
| parent | 10e3ca2cc19678c83378befc6be0feb31e0b2ebc (diff) | |
| download | bcm5719-llvm-915c5ecee16658544c5a35eabd7cbc404cdedd0d.tar.gz bcm5719-llvm-915c5ecee16658544c5a35eabd7cbc404cdedd0d.zip | |
[PPC] Legalize FNEG on PPC when possible
Currently we always expand ISD::FNEG. For v4f32 and v2f64 vector types VSX has
native support for this opcode
Phabricator: http://reviews.llvm.org/D17647
llvm-svn: 262079
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 731bae4c3f0..59086f1cbb9 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -647,6 +647,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom); + setOperationAction(ISD::FNEG, MVT::v4f32, Legal); + setOperationAction(ISD::FNEG, MVT::v2f64, Legal); + addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); } |
