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* Revert "Revert r330403 and r330413."Michael Zolotukhin2018-04-202-39/+42
| | | | | | | | | | | Reapply the patches with a fix. Thanks Ilya and Hans for the reproducer! This reverts commit r330416. The issue was that removing predecessors invalidated uses that we stored for rewrite. The fix is to finish manipulating with CFG before we select uses for rewrite. llvm-svn: 330431
* [X86][BtVer2] Cleanup some old FIXMEs from the model. NFCI.Simon Pilgrim2018-04-201-5/+2
| | | | llvm-svn: 330428
* [X86] Tag CLDEMOTE instruction with WriteLoad scheduling classSimon Pilgrim2018-04-201-1/+2
| | | | | | Same as other cacheline instructions llvm-svn: 330424
* [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load ↵Sander de Smalen2018-04-203-2/+53
| | | | | | | | | | | | | | | | | | | instructions. This is patch [4/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45690 llvm-svn: 330423
* [ObjectYAML] Add ability for DWARFYAML to calculate DIE lengthsJonas Devlieghere2018-04-201-4/+46
| | | | | | | | | | | | | | | | | | | | This patch adds the ability for the ObjectYAML DWARFEmitter to calculate the lengths of DIEs. This is accomplished by creating a DIEFixupVisitor class which traverses the DWARF DIEs to calculate and fix up the lengths in the Compile Unit header. The DIEFixupVisitor can be extended in the future to enable more complex fix ups which will enable simplified YAML string representations. This is also very useful when using the YAML format in unit tests because you no longer need to know the length of the compile unit when writing the YAML string. Differential commandeered from Chris Bieneman (beanz) Differential revision: https://reviews.llvm.org/D30666 llvm-svn: 330421
* Revert r330403 and r330413.Ilya Biryukov2018-04-202-32/+29
| | | | | | | | | | | | | | | | Revert r330413: "[SSAUpdaterBulk] Use SmallVector instead of DenseMap for storing rewrites." Revert r330403 "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time." r330403 commit seems to crash clang during our integrate while doing PGO build with the following stacktrace: #2 llvm::SSAUpdaterBulk::RewriteAllUses(llvm::DominatorTree*, llvm::SmallVectorImpl<llvm::PHINode*>*) #3 llvm::JumpThreadingPass::ThreadEdge(llvm::BasicBlock*, llvm::SmallVectorImpl<llvm::BasicBlock*> const&, llvm::BasicBlock*) #4 llvm::JumpThreadingPass::ProcessThreadableEdges(llvm::Value*, llvm::BasicBlock*, llvm::jumpthreading::ConstantPreference, llvm::Instruction*) #5 llvm::JumpThreadingPass::ProcessBlock(llvm::BasicBlock*) The crash happens while compiling 'lib/Analysis/CallGraph.cpp'. r3340413 is reverted due to conflicting changes. llvm-svn: 330416
* [SSAUpdaterBulk] Use SmallVector instead of DenseMap for storing rewrites.Michael Zolotukhin2018-04-202-16/+13
| | | | llvm-svn: 330413
* [LTO] Add stats-file option to LTO/Config.h.Florian Hahn2018-04-201-3/+21
| | | | | | | | | | | | | This patch adds a StatsFile option to LTO/Config.h and updates both LLVMGold and llvm-lto2 to set it. Reviewers: MatzeB, tejohnson, espindola Reviewed By: tejohnson Differential Revision: https://reviews.llvm.org/D45531 llvm-svn: 330411
* [AArch64][SVE] Fix diagnostic for SVE LD4 instructions:Sander de Smalen2018-04-201-1/+1
| | | | | | | | | | Diagnostic: 'index must be multiple of 3 in range [-32, 28]' Must be: 'index must be multiple of 4 in range [-32, 28]' llvm-svn: 330407
* [AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted register classes.Sander de Smalen2018-04-205-7/+88
| | | | | | | | | | | | | | | | | | | | Summary: This is patch [3/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: SjoerdMeijer Subscribers: tschuett, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45689 llvm-svn: 330406
* Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." one more time.Michael Zolotukhin2018-04-201-16/+22
| | | | | | | | | Hopefully, changing set to vector removes nondeterminism detected by some bots, or the new assert will catch something. This reverts commit r330180. llvm-svn: 330403
* [SSAUpdaterBulk] Add an assert.Michael Zolotukhin2018-04-201-0/+1
| | | | llvm-svn: 330402
* [SSAUpdaterBulk] Add * and & to auto.Michael Zolotukhin2018-04-201-4/+4
| | | | llvm-svn: 330400
* [SSAUpdaterBulk] Use PredCache in ComputeLiveInBlocks.Michael Zolotukhin2018-04-201-3/+4
| | | | llvm-svn: 330399
* [SSAUpdaterBulk] Use SmallVector instead of SmallPtrSet for uses.Michael Zolotukhin2018-04-201-2/+5
| | | | llvm-svn: 330398
* Revert "This pass, fixing an erratum in some LEON 2 processors..."Daniel Cederman2018-04-205-18/+1
| | | | | | | | | | | | | | | | | | | | | Summary: Reading Atmel's AT697E errata document this does not seem like a valid workaround. While the text only mentions SDIV, it says that the ICC flags can be wrong, and those are only generated by SDIVcc. Verification on hardware shows that simply replacing SDIV with SDIVcc does not avoid the bug with negative operands. This reverts r283727. Reviewers: lero_chris, jyknight Reviewed By: jyknight Subscribers: fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45813 llvm-svn: 330397
* [Sparc] Use synthetic instruction clr to zero register instead of sethiDaniel Cederman2018-04-201-0/+3
| | | | | | | | | | | | | | | Using `clr reg`/`mov %g0, reg`/`or %g0, %g0, reg` to zero a register looks much better than `sethi 0, reg`. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45810 llvm-svn: 330396
* [AArch64][AsmParser] Extend RegOp with integrated 'shift/extend'.Sander de Smalen2018-04-202-36/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In some cases the shift/extend needs to be explicitly parsed together with the register, rather than as a separate operand. This is needed for addressing modes where the instruction as a whole dictates the scaling/extend, rather than specific bits in the instruction. By parsing them as a single operand, we avoid the need to pass an extra operand in all CodeGen patterns (because all operands need to have an associated value), and we avoid the need to update TableGen to accept operands that have no associated bits in the instruction. An added benefit of parsing them together is that the assembler can give a sensible diagnostic if the scaling is not correct. This is patch [2/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro Reviewed By: fhahn, SjoerdMeijer Subscribers: kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45688 llvm-svn: 330394
* AMDGPU: Legalize the operand of SI_INIT_M0Nicolai Haehnle2018-04-201-0/+15
| | | | | | | | | | | | | | | | | | | | Summary: This fixes a case where the argument to a sendmsg intrinsic ends up in a VGPR, for whatever reason. The underlying performance issue is that a multiplication that can be an s_mul_i32 is instead needlessly generated as v_mul_u32_u24, but this is not addressed by this patch. Change-Id: I61fd4034314d5acdf6074632c30b65364dfa7328 Reviewers: arsenm, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45826 llvm-svn: 330393
* [Sparc] Fix addressing mode when using 64-bit values in inline assemblyDaniel Cederman2018-04-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If a 64-bit register is used as an operand in inline assembly together with a memory reference, the memory addressing will be wrong. The addressing will be a single reg, instead of reg+reg or reg+imm. This will generate a bad offset value or an exception in printMemOperand(). For example: ``` long long int val = 5; long long int mem; __asm__ volatile ("std %1, %0":"=m"(mem):"r"(val)); ``` becomes: ``` std %i0, [%i2+589833] ``` The problem is that SelectInlineAsmMemoryOperand() is never called for the memory references if one of the operands is a 64-bit register. By calling SelectInlineAsmMemoryOperands() in tryInlineAsm() the Sparc version of SelectInlineAsmMemoryOperand() gets called for each memory reference. Reviewers: jyknight, venkatra Reviewed By: jyknight Subscribers: eraman, fedor.sergeev, jrtc27, llvm-commits Differential Revision: https://reviews.llvm.org/D45761 llvm-svn: 330392
* LowerTypeTests: Propagate symver directivesVlad Tsyrklevich2018-04-205-38/+103
| | | | | | | | | | | | | | | | | | | | | | Summary: This change fixes https://crbug.com/834474, a build failure caused by LowerTypeTests not preserving .symver symbol versioning directives for exported functions. Emit symver information to ThinLTO summary data and then propagate symver directives for exported functions to the merged module. Emitting symver information to the summaries increases the size of intermediate build artifacts for a Chromium build by less than 0.2%. Reviewers: pcc Reviewed By: pcc Subscribers: tejohnson, mehdi_amini, eraman, llvm-commits, eugenis, kcc Differential Revision: https://reviews.llvm.org/D45798 llvm-svn: 330387
* Move a dump() implementation out of line.Amara Emerson2018-04-201-0/+11
| | | | | | Fixes some link issues. llvm-svn: 330384
* [MachineOutliner] NFC: Move EnableLinkOnceODROutlining into MachineOutliner.cppJessica Paquette2018-04-192-10/+20
| | | | | | | | | This moves the EnableLinkOnceODROutlining flag from TargetPassConfig.cpp into MachineOutliner.cpp. It also removes OutlineFromLinkOnceODRs from the MachineOutliner constructor. This is now handled by the moved command-line flag. llvm-svn: 330373
* [WebAssembly] Enabled -triple=wasm32-unknown-unknown-wasm path using ELF ↵Sam Clegg2018-04-191-3/+7
| | | | | | | | | | | | | | | | directive parser. This is a temporary solution until a proper WASM implementation of MCAsmParserExtension is in place, but at least for now will unblock this path. Added test to make sure this path works with the WASM Assembler. Patch By Wouter van Oortmerssen! Differential Revision: https://reviews.llvm.org/D45386 llvm-svn: 330370
* [AMDGPU] Use packed literals with zero either lower or hi partStanislav Mekhanoshin2018-04-192-2/+21
| | | | | | Differential Revision: https://reviews.llvm.org/D45790 llvm-svn: 330365
* Refine the loop rotation's APIJin Lin2018-04-192-12/+21
| | | | | | | | | | | | | | | | Summary: The following changes addresses the following two issues. 1) The existing loop rotation pass contains both loop latch simplification and loop rotation. So one flag RotationOnly is added to be passed to the loop rotation pass. 2) The threshold value is initialized with MAX_UINT since the loop rotation utility should not have threshold limit. Reviewers: dmgreen, efriedma Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D45582 llvm-svn: 330362
* [ORC] Fix an assertion condition from r329934.Lang Hames2018-04-191-2/+2
| | | | | | Thanks to Alexander Ivchenko for finding the issue! llvm-svn: 330359
* [X86] Enable popcnt false dependency breaking on Silvermont and Goldmont.Craig Topper2018-04-191-2/+6
| | | | | | Silvermont and Goldmont have the same issue on popcnt as Sandy Bridge, Haswell, Broadwell, and Skylake. Believe it is fixed in Goldmont Plus. llvm-svn: 330358
* [PM/LoopUnswitch] Detect irreducible control flow within loops and skip ↵Chandler Carruth2018-04-191-0/+13
| | | | | | | | | | | | | | | | | | | | unswitching non-trivial edges. Summary: This fixes the bug pointed out in review with non-trivial unswitching. This also provides a basis that should make it pretty easy to finish fleshing out a routine to scan an entire function body for irreducible control flow, but this patch remains minimal for disabling loop unswitch. Reviewers: sanjoy, fedor.sergeev Subscribers: mcrosier, hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D45754 llvm-svn: 330357
* [ORC] Make VSO symbol resolution/finalization operations private.Lang Hames2018-04-191-85/+109
| | | | | | | | This forces these operations to be carried out via a MaterializationResponsibility instance, ensuring responsibility is explicitly tracked. llvm-svn: 330356
* [X86][SLM] Fix typo using SandyBridge resources. Simon Pilgrim2018-04-191-2/+2
| | | | | | Luckily this was on instructions not supported on Silvermont.... llvm-svn: 330351
* [X86] Correct the scheduling data for register forms of XCHG and XADD on ↵Craig Topper2018-04-195-22/+24
| | | | | | | | | | | | Intel CPUs. The XCHG16rr/XCHG32rr/XCHG64rr instructions should be 3 uops just like XCHG8rr. I believe they're just implemented as 3 move uops with a temporary register. XADD is probably 2 moves and an add also using a temporary register. Change the latency for both from 2 cycles to 3 cycles. Only 2 of the uops are serialized in their execution, the move into the temporary and the move out of the temporary. The move from one GPR to the other should be able to go in parallel with this if there are ALU resources available. llvm-svn: 330349
* [Reassociate] fix formatting; NFCSanjay Patel2018-04-191-4/+3
| | | | llvm-svn: 330348
* [X86] Merge some MMX instregexSimon Pilgrim2018-04-195-269/+88
| | | | | | There's a lot more but I'd prefer focussing on removing unnecessary InstRWs first. llvm-svn: 330347
* [if-converter] Handle BBs that terminate in ret during diamond conversionKrzysztof Parzyszek2018-04-191-11/+28
| | | | | | | | | | This fixes https://llvm.org/PR36825. Original patch by Valentin Churavy (D45218). Differential Revision: https://reviews.llvm.org/D45731 llvm-svn: 330345
* [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTORKrzysztof Parzyszek2018-04-191-0/+26
| | | | llvm-svn: 330344
* [llvm-objdump] Print "..." instead of random data for virtual sectionsFrancis Visoiu Mistrih2018-04-191-2/+4
| | | | | | | | | | | | | | | | | When disassembling with -D, skip virtual sections by printing "..." for each symbol. This patch also implements `MachOObjectFile::isSectionVirtual`. Test case comes from: ``` .zerofill __DATA,__common,_data64unsigned,472,3 ``` Differential Revision: https://reviews.llvm.org/D45824 llvm-svn: 330342
* [AMDGPU] Do not only rely on BB number when finding bottom loopMark Searles2018-04-191-20/+45
| | | | | | | | We should also check that the "bottom" basic block of a loopis a successor of the "header" basic block, otherwise we don't propagate the information correctly when the CFG is complex. This fixes an important rendering problem with Wolfsentein 2, because of one vector-memory wait was missing. Differential Revision: https://reviews.llvm.org/D43831 llvm-svn: 330337
* [NewGVN] Add ops as dependency if we cannot find a leader for ValueOp.Florian Hahn2018-04-191-2/+11
| | | | | | | | | | | | | | | | | If those operands change, we might find a leader for ValueOp, which could enable new phi-of-op creation. This fixes a case where we missed creating a phi-of-ops node. With D43865 and this patch, bootstrapping clang/llvm works with -enable-newgvn, whereas without it, the "value changed after iteration" assertion is triggered. Reviewers: dberlin, davide Reviewed By: dberlin Differential Revision: https://reviews.llvm.org/D42180 llvm-svn: 330334
* [Hexagon] Generate code for vector bswap intrinsicsKrzysztof Parzyszek2018-04-191-0/+5
| | | | llvm-svn: 330333
* [X86][BtVer2] Remove SSE4A EXTRQ/EXTRQI InstRW overrides.Simon Pilgrim2018-04-191-4/+0
| | | | | | These are already handled identically by WriteALU. llvm-svn: 330332
* [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical opsKrzysztof Parzyszek2018-04-192-99/+89
| | | | llvm-svn: 330330
* [mips] Correct the definitions of the unaligned word memory operation ↵Simon Dardis2018-04-194-25/+40
| | | | | | | | | | | | | | | | instructions These instructions lacked the correct predicates, were not marked as loads and stores and lacked the proper instruction mapping information. In the case of microMIPS sw(l|r)e (EVA) these instructions were using the load EVA description. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45626 llvm-svn: 330326
* Lowering x86 adds/addus/subs/subus intrinsics (llvm part)Alexander Ivchenko2018-04-193-42/+193
| | | | | | | | | | | | | This is the patch that lowers x86 intrinsics to native IR in order to enable optimizations. The patch also includes folding of previously missing saturation patterns so that IR emits the same machine instructions as the intrinsics. Patch by tkrupa Differential Revision: https://reviews.llvm.org/D44785 llvm-svn: 330322
* [X86][FMA] Remove FMA reg-reg InstRW scheduler overrides.Simon Pilgrim2018-04-194-25/+1
| | | | | | These are all already handled identically by WriteFMA. llvm-svn: 330319
* [X86][BtVer2] Remove 128-bit F16C InstRW overrides.Simon Pilgrim2018-04-191-10/+0
| | | | | | These are already handled identically by WriteCvtF2F. llvm-svn: 330318
* [BasicBlock] Add instructionsWithoutDebug methods to skip debug insts.Florian Hahn2018-04-191-0/+18
| | | | | | | | | | Reviewers: aprantl, vsk, mattd, chandlerc Reviewed By: aprantl, vsk Differential Revision: https://reviews.llvm.org/D45657 llvm-svn: 330316
* [mips] Guard some macro expansions properlySimon Dardis2018-04-193-20/+24
| | | | | | | | Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D45565 llvm-svn: 330315
* [AArch64][AsmParser] NFC: Cleanup parsing of scalar registers.Sander de Smalen2018-04-191-77/+69
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: - Renamed tryParseRegister to tryParseScalarRegister, which now returns an OperandMatchResultTy. - Moved matching of certain aliases into matchRegisterNameAlias. - Changed type of most 'Reg' variables to 'unsigned'. This is patch [1/4] in a series to add assembler/disassembler support for SVE's contiguous LD1 (scalar+scalar) instructions: - Patch [1/4]: https://reviews.llvm.org/D45687 - Patch [2/4]: https://reviews.llvm.org/D45688 - Patch [3/4]: https://reviews.llvm.org/D45689 - Patch [4/4]: https://reviews.llvm.org/D45690 Reviewers: fhahn, rengolin, javed.absar, huntergr, SjoerdMeijer, t.p.northover, echristo, evandro, samparker Reviewed By: samparker Subscribers: samparker, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D45687 llvm-svn: 330311
* [X86] Scrub scheduling information for MUL/IMUL on Intel CPUs.Craig Topper2018-04-195-35/+81
| | | | | | This removes a bunch of unnecessary InstRW overrides. It also cleans up the missing information from the Sandy Bridge model. Other fixes to other models. llvm-svn: 330308
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