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* [RegisterBankInfo] Add methods to get the possible mapping of an instruction ↵Quentin Colombet2016-04-061-0/+11
| | | | | | | | | on a register bank. This will be used by the register bank select pass to assign register banks for generic virtual registers. llvm-svn: 265573
* [AArch64] Change the CMake to avoid to build GlobalISel related APIsQuentin Colombet2016-04-062-18/+12
| | | | | | | | | | when GISel is not built. The positive side effects are: - We do not have to define dummy implementation - We do not have to do weird gymnastic to avoid like issues (like missing constructor or vtable for the base classes) llvm-svn: 265570
* [AArch64] Teach the subtarget how to get to the RegisterBankInfo.Quentin Colombet2016-04-064-6/+80
| | | | | | | | | | | Rework the access to GlobalISel APIs to contain how much of the APIs we need to access for the final executable to build when GlobalISel is not built. This prevents massive usage of ifdefs in various places. Now, all the GlobalISel ifdefs will be happing only in AArch64TargetMachine.cpp. llvm-svn: 265567
* [RegisterBankInfo] Implement the verify method of the InstructionMapping ↵Quentin Colombet2016-04-061-0/+25
| | | | | | | | helper class. This checks that all the register operands get a proper mapping. llvm-svn: 265563
* Loop Unroll: add options and tweak to make Partial unrolling more usefulFiona Glaser2016-04-061-3/+20
| | | | | | | | | | | | | | | | 1. Add FullUnrollMaxCount option that works like MaxCount, but also limits the unroll count for fully unrolled loops. So if a loop has an iteration count over this, it won't fully unroll. 2. Add CLI options for MaxCount and the new option, so they can be tested (plus a test). 3. Make partial unrolling obey MaxCount. An example use-case (the out of tree one this is originally designed for) is a target’s TTI can analyze a loop and decide on a max unroll count separate from the size threshold, e.g. based on register pressure, then constrain LoopUnroll to not exceed that, regardless of the size of the unrolled loop. llvm-svn: 265562
* Revert r265450 "[X86] Reuse EFLAGS and form LOCKed ops when only user is SETCC."Hans Wennborg2016-04-061-76/+15
| | | | | | It caused ASan 32-bit tests to hang (PR27245). llvm-svn: 265559
* LoopUnroll: only allow non-modulo Partial unrolling when Runtime=trueFiona Glaser2016-04-061-2/+4
| | | | | | Patch by Evgeny Stupachenko <evstupac@gmail.com>. llvm-svn: 265558
* [RegisterBankInfo] Implement the verify method for the ValueMapping helper ↵Quentin Colombet2016-04-061-4/+16
| | | | | | | | | class. The method checks that the value is fully defined accross the different partial mappings and that the partial mappings are compatible between each other. llvm-svn: 265556
* [RegisterBankInfo] Add a verify method for the PartialMapping helper class.Quentin Colombet2016-04-061-0/+19
| | | | | | | This verifies that the PartialMapping can be accomadated into the related register bank. llvm-svn: 265555
* [RegisterBankInfo] Add a couple of helper classes for the future cost model.Quentin Colombet2016-04-061-0/+31
| | | | llvm-svn: 265553
* Revert "Re-commit r265039 "[X86] Merge adjacent stack adjustments in ↵Hans Wennborg2016-04-061-26/+13
| | | | | | | | | eliminateCallFramePseudoInstr (PR27140)"" It seems to be causing ASan tests to crash, probably due to miscompiling the run-time somehow. llvm-svn: 265551
* [AArch64] Use the default constructor of RegisterBankInfo when GlobalISel is ↵Quentin Colombet2016-04-061-1/+1
| | | | | | | | | not built. This will avoid link-time error as the defautl constructor of RegisterBankInfo is the only one available when GlobalISel is not built. llvm-svn: 265549
* [RegisterBankInfo] Inline the destructor to avoid link-time error when ↵Quentin Colombet2016-04-061-2/+0
| | | | | | GlobalISel is not built. llvm-svn: 265548
* Recommit r265309 after fixed an invalid memory reference bug happenedWei Mi2016-04-0610-526/+714
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when DenseMap growed and moved memory. I verified it fixed the bootstrap problem on x86_64-linux-gnu but I cannot verify whether it fixes the bootstrap error on clang-ppc64be-linux. I will watch the build-bot result closely. Replace analyzeSiblingValues with new algorithm to fix its compile time issue. The patch is to solve PR17409 and its duplicates. analyzeSiblingValues is a N x N complexity algorithm where N is the number of siblings generated by reg splitting. Although it causes siginificant compile time issue when N is large, it is also important for performance since it removes redundent spills and enables rematerialization. To solve the compile time issue, the patch removes analyzeSiblingValues and replaces it with lower cost alternatives containing two parts. The first part creates a new spill hoisting method in postOptimization of register allocation. It does spill hoisting at once after all the spills are generated instead of inside every instance of selectOrSplit. The second part queries the define expr of the original register for rematerializaiton and keep it always available during register allocation even if it is already dead. It deletes those dead instructions only in postOptimization. With the two parts in the patch, it can remove analyzeSiblingValues without sacrificing performance. Differential Revision: http://reviews.llvm.org/D15302 llvm-svn: 265547
* Revert r265535 until we know how we can fix the bots Silviu Baranga2016-04-064-236/+91
| | | | llvm-svn: 265541
* [AMDGPU] AsmParser: disable DPP for unsupported instructions. New dpp tests. ↵Sam Kolton2016-04-062-11/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix v_nop_dpp. Summary: 1. Disable DPP encoding for instructions that do not support it: - VOP1: - v_readfirstlane_b32 - v_clrexcp - v_movreld_b32 - v_movrels_b32 - v_movrelsd_b32 - VOP2: - v_madmk_f16/32 - v_madak_f16/32 - VOPC, VINTRP, VOP3 2. Fix DPP for v_nop 3. New DPP tests for VOP1 and VOP2 instructions Reviewers: nhaustov, tstellarAMD, vpykhtin Subscribers: tstellarAMD, arsenm Differential Revision: http://reviews.llvm.org/D18552 llvm-svn: 265538
* Simplify logic. NFC.Chad Rosier2016-04-061-7/+5
| | | | llvm-svn: 265537
* [SCEV] Introduce a guarded backedge taken count and use it in LAA and LVSilviu Baranga2016-04-064-91/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When the backedge taken codition is computed from an icmp, SCEV can deduce the backedge taken count only if one of the sides of the icmp is an AddRecExpr. However, due to sign/zero extensions, we sometimes end up with something that is not an AddRecExpr. However, we can use SCEV predicates to produce a 'guarded' expression. This change adds a method to SCEV to get this expression, and the SCEV predicate associated with it. In HowManyGreaterThans and HowManyLessThans we will now add a SCEV predicate associated with the guarded backedge taken count when the analyzed SCEV expression is not an AddRecExpr. Note that we only do this as an alternative to returning a 'CouldNotCompute'. We use new feature in Loop Access Analysis and LoopVectorize to analyze and transform more loops. Reviewers: anemet, mzolotukhin, hfinkel, sanjoy Subscribers: flyingforyou, mcrosier, atrick, mssimpso, sanjoy, mzolotukhin, llvm-commits Differential Revision: http://reviews.llvm.org/D17201 llvm-svn: 265535
* [AArch64][CodeGen] NFC refactor AArch64InstrInfo::optimizeCompareInstr to ↵Evgeny Astigeevich2016-04-062-57/+101
| | | | | | | | | | | | | | | | | | | prepare it for fixing a bug in it AArch64InstrInfo::optimizeCompareInstr has a bug which causes generation of incorrect code (PR#27158). The patch refactors the function to simplify reviewing the fix of the bug. 1. Function name ‘modifiesConditionCode’ is changed to ‘areCFlagsAccessedBetweenInstrs’ to reflect that the function can check modifying accesses, reading accesses or both. 2. Function ‘AArch64InstrInfo::optimizeCompareInstr’ - Documented the function - Cmp_NZCV is DeadNZCVIdx to reflect that it is an operand index of dead NZCV - The code for the case of substituting CmpInstr is put into separate functions the main of them is ‘substituteCmpInstr’. Differential Revision: http://reviews.llvm.org/D18609 llvm-svn: 265531
* [ppc64] Temporary disable sibling call optimization on ppc64 due to breaking ↵Chuang-Yu Cheng2016-04-061-1/+1
| | | | | | | | | | | test case r265506 breaks print-stack-trace.cc test case of compiler-rt in bootstrap test. http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/1708 llvm-svn: 265528
* [SLPVectorizer] Vectorizing the libm sqrt to llvm's sqrt intrinsic requires nnanDavid Majnemer2016-04-061-1/+3
| | | | | | | | | | | | | | To quote the langref "Unlike sqrt in libm, however, llvm.sqrt has undefined behavior for negative numbers other than -0.0 (which allows for better optimization, because there is no need to worry about errno being set). llvm.sqrt(-0.0) is defined to return -0.0 like IEEE sqrt." This means that it's unsafe to replace sqrt with llvm.sqrt unless the call is annotated with nnan. Thanks to Hal Finkel for pointing this out! llvm-svn: 265521
* IR: Move MDStrings to a BumpPtrAllocatorDuncan P. N. Exon Smith2016-04-061-1/+1
| | | | | | | We never delete any MDString until the context is destroyed. Might as well throw them onto a BumpPtrAllocator. llvm-svn: 265520
* IRMover: Steal arguments when moving functions, NFCDuncan P. N. Exon Smith2016-04-062-19/+28
| | | | | | | | | | | | | | | | | | Instead of copying arguments from the source function to the destination, steal them. This has a few advantages. - The ValueMap doesn't need to be seeded with (or cleared of) Arguments. - Often the destination function won't have created any arguments yet, so this avoids malloc traffic. - Argument names don't need to be copied. Because argument lists are lazy, this required a new Function::stealArgumentListFrom helper. llvm-svn: 265519
* Revert "[IRVerifier] Don't crash on invalid DIFile inside DISubprogram."Davide Italiano2016-04-061-2/+0
| | | | | | | This reverts commit r265515 as lots of tests need to be fixed before this actually can go in. llvm-svn: 265517
* Add parentheses to silence warning.Richard Trieu2016-04-061-1/+2
| | | | llvm-svn: 265516
* [IRVerifier] Don't crash on invalid DIFile inside DISubprogram.Davide Italiano2016-04-061-0/+2
| | | | llvm-svn: 265515
* [IRVerifier] Avoid crashing on an invalid compile unit.Davide Italiano2016-04-061-7/+8
| | | | llvm-svn: 265514
* AArch64: Fix compile errorMatthias Braun2016-04-061-1/+1
| | | | | | | Fixed to adapt a use of enterBasicBlock() in my last commit (because I had follow on patches in my repository that change the code). llvm-svn: 265513
* RegisterScavenger: Take a reference as enterBasicBlock() argument.Matthias Braun2016-04-069-17/+14
| | | | | | | Make it obvious that the argument cannot be nullptr. Remove an unnecessary nullptr check in initRegState. llvm-svn: 265511
* LivePhysRegs: Remove redundant checkMatthias Braun2016-04-061-1/+1
| | | | llvm-svn: 265509
* ValueMapper: Fix delayed blockaddress handling after r265273Duncan P. N. Exon Smith2016-04-061-3/+3
| | | | | | | | | r265273 added Mapper::mapBlockAddress, which delays mapping a blockaddress value until the function has a body. The condition was backwards, and should be checking Function::empty instead of GlobalValue::isDeclaration. llvm-svn: 265508
* AsmParser: Don't crash on unresolved !tbaaDuncan P. N. Exon Smith2016-04-061-4/+5
| | | | | | | | Instead of crashing, give a nice error. As a drive-by, fix the location associated with the errors for unresolved metadata (the location was off by one token). llvm-svn: 265507
* [ppc64] Enable sibling call optimization on ppc64 ELFv1/ELFv2 abiChuang-Yu Cheng2016-04-062-7/+228
| | | | | | | | | | | | | | | | | This patch enable sibling call optimization on ppc64 ELFv1/ELFv2 abi, and add a couple of test cases. This patch also passed llvm/clang bootstrap test, and spec2006 build/run/result validation. Original issue: https://llvm.org/bugs/show_bug.cgi?id=25617 Great thanks to Tom's (tjablin) help, he contributed a lot to this patch. Thanks Hal and Kit's invaluable opinions! Reviewers: hfinkel kbarton http://reviews.llvm.org/D16315 llvm-svn: 265506
* [Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random ↵Chuang-Yu Cheng2016-04-067-0/+269
| | | | | | | | | | | | | | | | | | | | | number, set bool, and dfp test significance This patch implement the following instructions: - addpcis subpcis - maddhd maddhdu maddld - modsw moduw modsd modud - darn - extswsli extswsli. - setb - dtstsfi dtstsfiq Total 15 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton http://reviews.llvm.org/D17885 llvm-svn: 265505
* [Power9] Implement copy-paste, msgsync, slb, and stop instructionsChuang-Yu Cheng2016-04-066-0/+109
| | | | | | | | | | | | | This patch implements the following BookII and Book III instructions: - copy copy_first cp_abort paste paste. paste_last - msgsync - slbieg slbsync - stop Total 10 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton llvm-svn: 265504
* [RS4GC] Add a commentSanjoy Das2016-04-061-0/+4
| | | | llvm-svn: 265503
* Lower @llvm.experimental.deoptimize as a noreturn callSanjoy Das2016-04-063-7/+35
| | | | | | | | | | | | | | | | | | | | | | | While preserving the return value for @llvm.experimental.deoptimize at the IR level is useful during mid-level optimization, doing so at the machine instruction level requires generating some extra code and a return that is non-ideal. This change has LLVM lower ``` %val = call @llvm.experimental.deoptimize ret %val ``` to effectively ``` call @__llvm_deoptimize() unreachable ``` instead. llvm-svn: 265502
* AArch64CodeGen: Make AArch64RegisterBankInfo.cpp optional along ↵NAKAMURA Takumi2016-04-061-1/+13
| | | | | | LLVM_BUILD_GLOBAL_ISEL. llvm-svn: 265499
* [SLPVectorizer] Vectorize libcalls of sqrtDavid Majnemer2016-04-061-0/+4
| | | | | | | We didn't realize that we could transform the libcall into a vectorized intrinsic. llvm-svn: 265493
* [AArch64] Initial implementation of the targeting of the register bank ↵Quentin Colombet2016-04-053-0/+115
| | | | | | information. llvm-svn: 265489
* [RegisterBankInfo] Simplify the API for build a register bank.Quentin Colombet2016-04-051-5/+4
| | | | | | | | | As part of the TRI argument of addRegBankCoverage we already have access to the TargetRegisterClass through the ID of that register class. Therefore, there is no point in needing a TargetRegisterClass instance, the ID is enough to get to it. llvm-svn: 265487
* [RS4GC] NFC cleanup of the DeferredReplacement classSanjoy Das2016-04-051-5/+18
| | | | | | Instead of constructors use clearly named factory methods. llvm-svn: 265486
* [RS4GC] Better codegen for deoptimize callsSanjoy Das2016-04-051-16/+52
| | | | | | | | | Don't emit a gc.result for a statepoint lowered from @llvm.experimental.deoptimize since the call into __llvm_deoptimize is effectively noreturn. Instead follow the corresponding gc.statepoint with an "unreachable". llvm-svn: 265485
* Swift Calling Convention: swiftcc for ARM.Manman Ren2016-04-052-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D18769 llvm-svn: 265482
* Faster stack-protector for Android/AArch64.Evgeniy Stepanov2016-04-055-27/+42
| | | | | | | Bionic has a defined thread-local location for the stack protector cookie. Emit a direct load instead of going through __stack_chk_guard. llvm-svn: 265481
* Swift Calling Convention: add swiftcc.Manman Ren2016-04-056-0/+27
| | | | | | Differential Revision: http://reviews.llvm.org/D17863 llvm-svn: 265480
* [RegisterBank] Implement the verify method to check for the obvious mistakes.Quentin Colombet2016-04-051-4/+27
| | | | llvm-svn: 265479
* [RegisterBankInfo] Add debug print to check how the initialization is going.Quentin Colombet2016-04-051-0/+11
| | | | llvm-svn: 265475
* [CFLAA] Fix PR27213; incorrect tagging of args/globalsGeorge Burgess IV2016-04-051-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this patch, CFLAA wouldn't tag arguments/globals properly if it didn't find any "interesting" edges on them. This means that, if all you do is store constants to a global or argument, we would never actually treat it as a global/argument. Test case: define void @foo(i32* %A, i32* %B) #0 { entry: store i32 0, i32* %A, align 4 store i32 0, i32* %B, align 4 ret void } CFLAA would say that %A can't alias %B, because neither pointer was used in an interesting way. This patch makes us note whether something is an argument, global, ... regardless of how interesting CFLAA thinks its uses are. (For the record, using a value in an interesting way means loading from it, using it in a GEP, ...) llvm-svn: 265474
* [RegisterBank] Add printable capabilities for future debugging.Quentin Colombet2016-04-051-0/+34
| | | | llvm-svn: 265473
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