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| author | Quentin Colombet <qcolombet@apple.com> | 2016-04-06 16:27:01 +0000 | 
|---|---|---|
| committer | Quentin Colombet <qcolombet@apple.com> | 2016-04-06 16:27:01 +0000 | 
| commit | 89c33caee358da59b7e8d1876bb117b3220aae98 (patch) | |
| tree | 94253bb3659cb491f428d6b98c0827035fa81d2d /llvm/lib | |
| parent | a7e396b5ef430f7ce375175cd021b0a0a8bfa8d1 (diff) | |
| download | bcm5719-llvm-89c33caee358da59b7e8d1876bb117b3220aae98.tar.gz bcm5719-llvm-89c33caee358da59b7e8d1876bb117b3220aae98.zip | |
[RegisterBankInfo] Add a couple of helper classes for the future cost model.
llvm-svn: 265553
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp | 31 | 
1 files changed, 31 insertions, 0 deletions
| diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp index 3039ac9d831..d882779a0f5 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp @@ -11,9 +11,11 @@  //===----------------------------------------------------------------------===//  #include "llvm/CodeGen/GlobalISel/RegisterBank.h" +#include "llvm/ADT/SmallString.h"  #include "llvm/ADT/SmallVector.h"  #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"  #include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h"  #include "llvm/Target/TargetRegisterInfo.h"  #include <algorithm> // For std::max. @@ -170,3 +172,32 @@ void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId,        DEBUG(dbgs() << '\n');    } while (!WorkList.empty());  } + +//------------------------------------------------------------------------------ +// Helper classes implementation. +//------------------------------------------------------------------------------ +void RegisterBankInfo::PartialMapping::dump() const { +  print(dbgs()); +  dbgs() << '\n'; +} + +void RegisterBankInfo::PartialMapping::print(raw_ostream &OS) const { +  SmallString<128> MaskStr; +  Mask.toString(MaskStr, /*Radix*/ 2, /*Signed*/ 0, /*formatAsCLiteral*/ true); +  OS << "Mask(" << Mask.getBitWidth() << ") = " << MaskStr << ", RegBank = "; +  if (RegBank) +    OS << *RegBank; +  else +    OS << "nullptr"; +} + +void RegisterBankInfo::ValueMapping::verify() const { +  // Check that all the partial mapping have the same bitwidth. +  // Check that the union of the partial mappings covers the whole value. +  // Check that each register bank is big enough to hold the partial value. +} + +void RegisterBankInfo::InstructionMapping::verify( +    const MachineInstr &MI) const { +  // Check that all the register operands are properly mapped. +} | 

