[RegisterBankInfo] Add methods to get the possible mapping of an instruction on a register bank.

This will be used by the register bank select pass to assign register banks
for generic virtual registers.

llvm-svn: 265573

1 files changed, 11 insertions, 0 deletions

diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index 6e8307917c7..ee00894ccd9 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -19,6 +19,7 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetOpcodes.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 
 #include <algorithm> // For std::max.
@@ -27,6 +28,8 @@
 
 using namespace llvm;
 
+const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
+
 RegisterBankInfo::RegisterBankInfo(unsigned NumRegBanks)
     : NumRegBanks(NumRegBanks) {
   RegBanks.reset(new RegisterBank[NumRegBanks]);
@@ -176,6 +179,14 @@ void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId,
   } while (!WorkList.empty());
 }
 
+RegisterBankInfo::InstructionMapping
+RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
+  if (MI.getOpcode() > TargetOpcode::GENERIC_OP_END) {
+    // TODO.
+  }
+  llvm_unreachable("The target must implement this");
+}
+
 //------------------------------------------------------------------------------
 // Helper classes implementation.
 //------------------------------------------------------------------------------