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* [SCEV] Refactor out a useful pattern; NFCSanjoy Das2016-11-091-134/+20
| | | | llvm-svn: 286386
* Revert r286384, "X86: Introduce the "relocImm" ComplexPattern, which ↵Peter Collingbourne2016-11-093-31/+52
| | | | | | | | | represents a relocatable immediate." Suspected to be the cause of a sanitizer-windows bot failure: Assertion failed: isImm() && "Wrong MachineOperand accessor", file C:\b\slave\sanitizer-windows\llvm\include\llvm/CodeGen/MachineOperand.h, line 420 llvm-svn: 286385
* X86: Introduce the "relocImm" ComplexPattern, which represents a relocatable ↵Peter Collingbourne2016-11-093-52/+31
| | | | | | | | | | | | | | | immediate. A relocatable immediate is either an immediate operand or an operand that can be relocated by the linker to an immediate, such as a regular symbol in non-PIC code. Start using relocImm for 32-bit and 64-bit MOV instructions, and for operands of type "imm32_su". Remove a number of now-redundant patterns. Differential Revision: https://reviews.llvm.org/D25812 llvm-svn: 286384
* [Hexagon] Silence "sometimes uninitialized" warning in HexagonCopyToCombineKrzysztof Parzyszek2016-11-091-1/+3
| | | | llvm-svn: 286383
* Bitcode: Change the materializer interface to return llvm::Error.Peter Collingbourne2016-11-0910-53/+63
| | | | | | Differential Revision: https://reviews.llvm.org/D26439 llvm-svn: 286382
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-0923-204/+255
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* [Hexagon] Eliminate Insert4 pseudo-instruction, use combines insteadKrzysztof Parzyszek2016-11-093-48/+2
| | | | llvm-svn: 286368
* [SystemZ] A few fixes in scheduler files.Jonas Paulsson2016-11-093-11/+11
| | | | | Review: U Weigand llvm-svn: 286362
* Remove TimeValue usage from Scalar/SROA.cpp. NFC.Pavel Labath2016-11-091-2/+3
| | | | llvm-svn: 286361
* Zero-initialize chrono duration objectsPavel Labath2016-11-091-1/+1
| | | | | | | The default duration constructor does not zero-initialize the object, we need to do that manually. llvm-svn: 286359
* [MachineScheduler] Comments fixing.Jonas Paulsson2016-11-092-2/+3
| | | | | | | | The name/comment of the third argument to the ScheduleDAGMI constructor is RemoveKillFlags and not IsPostRA. Only the comments are changed. Review: A Trick llvm-svn: 286350
* [ARM] Loop Strength Reduction crashes when targeting ARM or Thumb.Alexandros Lamprineas2016-11-091-3/+3
| | | | | | | | | | | Scalar Evolution asserts when not all the operands of an Add Recurrence Expression are loop invariants. Loop Strength Reduction should only create affine Add Recurrences, so that both the start and the step of the expression are loop invariants. Differential Revision: https://reviews.llvm.org/D26185 llvm-svn: 286347
* [AVX-512] Add lowering to cvttpd2udq/cvttps2udq for fptoui v2f64/2f32 to 2i32Craig Topper2016-11-095-8/+26
| | | | | | | | | | | | This patch adds support for fptoui to 2i32 from both 2f64 and 2f32, building on Simon's change for the signed version in r284459 and using AVX-512 instructions. If we don't have VLX support we need to use a 512-bit operation for v2f64->v2i32 and extract the result. It also recognises that cvttpd2udq zeroes the upper 64-bits of the xmm result. Differential Revision: https://reviews.llvm.org/D26331 llvm-svn: 286345
* [X86] Lower AVX512 and SSE intrinsics for CVTTPD2DQ to X86ISD::CVTTPD2DQ.Craig Topper2016-11-093-30/+34
| | | | | | | | | | | | Summary: This allows the SSE intrinsic to use the EVEX instruction when available. It also fixes EVEX to not use a weird (v4i32 (fp_to_sint v2f64)) node and it merges some isel patterns. This also fixes some cases that weren't combining vzmovl with cvttpd2dq to remove extra moves. Reviewers: delena, zvi, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26330 llvm-svn: 286344
* [AVX-512] Use alignedstore256 in patterns that look for stores of the lower ↵Craig Topper2016-11-091-10/+10
| | | | | | | | 256-bits of a 512-bit vector to use a 256-bit aligned store. Previously we were only checking for 16 byte alignment instead of 32 byte alignment. Fixes PR30947. llvm-svn: 286342
* [AVX-512] Make VBMI instruction set enabling imply that the BWI instruction ↵Craig Topper2016-11-091-2/+2
| | | | | | | | | | | | | | | set is also enabled. Summary: This is needed to make the v64i8 and v32i16 types legal for the 512-bit VBMI instructions. Fixes PR30912. Reviewers: delena, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26322 llvm-svn: 286339
* Revert "[ThinLTO] Prevent exporting of locals used/defined in module level asm"Mehdi Amini2016-11-094-76/+13
| | | | | | | | This reverts commit r286297. Introduces a dependency from libAnalysis to libObject, which I missed during the review. llvm-svn: 286329
* Bitcode: Remove the remnants of the BitcodeDiagnosticInfo class.Peter Collingbourne2016-11-091-2/+0
| | | | | | | | | The BitcodeReader no longer produces BitcodeDiagnosticInfo diagnostics. The only remaining reference was in the gold plugin; the code there has been dead since we stopped producing InvalidBitcodeSignature error codes in r225562. While at it remove the InvalidBitcodeSignature error code. llvm-svn: 286326
* Enable Loop Sink pass for functions that has profile.Dehao Chen2016-11-092-4/+9
| | | | | | | | | | | | Summary: For functions with profile data, we are confident that loop sink will be optimal in sinking code. Reviewers: davidxl, hfinkel Subscribers: mehdi_amini, mzolotukhin, llvm-commits Differential Revision: https://reviews.llvm.org/D26155 llvm-svn: 286325
* Bitcode: Change the BitcodeReader to use llvm::Error internally.Peter Collingbourne2016-11-091-339/+343
| | | | | | Differential Revision: https://reviews.llvm.org/D26430 llvm-svn: 286323
* [ValueTracking] recognize obfuscated variants of umin/umaxSanjay Patel2016-11-091-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The smallest tests that expose this are codegen tests (because SelectionDAGBuilder::visitSelect() uses matchSelectPattern to create UMAX/UMIN nodes), but it's also possible to see the effects in IR alone with folds of min/max pairs. If these were written as unsigned compares in IR, InstCombine canonicalizes the unsigned compares to signed compares. Ie, running the optimizer pessimizes the codegen for this case without this patch: define <4 x i32> @umax_vec(<4 x i32> %x) { %cmp = icmp ugt <4 x i32> %x, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> %sel = select <4 x i1> %cmp, <4 x i32> %x, <4 x i32> <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647> ret <4 x i32> %sel } $ ./opt umax.ll -S | ./llc -o - -mattr=avx vpmaxud LCPI0_0(%rip), %xmm0, %xmm0 $ ./opt -instcombine umax.ll -S | ./llc -o - -mattr=avx vpxor %xmm1, %xmm1, %xmm1 vpcmpgtd %xmm0, %xmm1, %xmm1 vmovaps LCPI0_0(%rip), %xmm2 ## xmm2 = [2147483647,2147483647,2147483647,2147483647] vblendvps %xmm1, %xmm0, %xmm2, %xmm0 Differential Revision: https://reviews.llvm.org/D26096 llvm-svn: 286318
* Added the ability to dump hex bytes easily into a raw_ostream.Greg Clayton2016-11-091-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unit tests were added to verify this functionality keeps working correctly. Example output for raw hex bytes: llvm::ArrayRef<uint8_t> Bytes = ...; llvm::outs() << format_hex_bytes(Bytes); 554889e5 4881ec70 04000048 8d051002 00004c8d 05fd0100 004c8b0d d0020000 Example output for raw hex bytes with offsets: llvm::outs() << format_hex_bytes(Bytes, 0x100000d10); 0x0000000100000d10: 554889e5 4881ec70 04000048 8d051002 0x0000000100000d20: 00004c8d 05fd0100 004c8b0d d0020000 Example output for raw hex bytes with ASCII with offsets: llvm::outs() << format_hex_bytes_with_ascii(Bytes, 0x100000d10); 0x0000000100000d10: 554889e5 4881ec70 04000048 8d051002 |UH.?H.?p...H....| 0x0000000100000d20: 00004c8d 05fd0100 004c8b0d d0020000 |..L..?...L..?...| The default groups bytes into 4 byte groups, but this can be changed to 1 byte: llvm::outs() << format_hex_bytes(Bytes, 0x100000d10, 16 /*NumPerLine*/, 1 /*ByteGroupSize*/); 0x0000000100000d10: 55 48 89 e5 48 81 ec 70 04 00 00 48 8d 05 10 02 0x0000000100000d20: 00 00 4c 8d 05 fd 01 00 00 4c 8b 0d d0 02 00 00 llvm::outs() << format_hex_bytes(Bytes, 0x100000d10, 16 /*NumPerLine*/, 2 /*ByteGroupSize*/); 0x0000000100000d10: 5548 89e5 4881 ec70 0400 0048 8d05 1002 0x0000000100000d20: 0000 4c8d 05fd 0100 004c 8b0d d002 0000 llvm::outs() << format_hex_bytes(Bytes, 0x100000d10, 8 /*NumPerLine*/, 1 /*ByteGroupSize*/); 0x0000000100000d10: 55 48 89 e5 48 81 ec 70 0x0000000100000d18: 04 00 00 48 8d 05 10 02 0x0000000100000d20: 00 00 4c 8d 05 fd 01 00 0x0000000100000d28: 00 4c 8b 0d d0 02 00 00 https://reviews.llvm.org/D26405 llvm-svn: 286316
* [InstCombine] fix profitability equation for max-of-nots transformSanjay Patel2016-11-091-7/+6
| | | | | | | | | | As the test change shows, we can increase the critical path by adding a 'not' instruction, so make sure that we're actually removing an instruction if we do this transform. This transform could also cause us to miss folds of min/max pairs. llvm-svn: 286315
* [InstCombine] reduce indentation; NFCSanjay Patel2016-11-081-23/+20
| | | | llvm-svn: 286314
* Fix some size_t / uint32_t ambiguity errors.Zachary Turner2016-11-081-7/+7
| | | | llvm-svn: 286305
* [CodeView] Hook up CodeViewRecordIO to type serialization path.Zachary Turner2016-11-0815-947/+485
| | | | | | | | | | | | Previously support had been added for using CodeViewRecordIO to read (deserialize) CodeView type records. This patch adds support for writing those same records. With this patch, reading and writing of CodeView type records finally uses a single codepath. Differential Revision: https://reviews.llvm.org/D26253 llvm-svn: 286304
* Emit the DW_AT_type for a C++ static member definitionAdrian Prantl2016-11-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | if it is more specific than the one in its DW_AT_specification. If a static member is an array, the translation unit containing the member definition may have a more specific type (including its length) than TUs only seeing the class declaration. This patch adds a DW_AT_type to the member's DW_TAG_variable in addition to the DW_AT_specification in these cases. The member type in the DW_AT_specification still shows the more generic type (without the length) to avoid defeating type uniquing. The DWARF standard discourages “duplicating” a DW_AT_type in a member variable definition but doesn’t explicitly forbid it. Having the more specific type (with the array length) available is what allows the debugger to print the contents of a static array member variable. https://reviews.llvm.org/D26368 rdar://problem/28706946 llvm-svn: 286302
* GlobalISel: make sure debugging variables are appropriately elided in ↵David L. Jones2016-11-081-2/+4
| | | | | | | | | | | | | | | | release builds. Summary: There are two variables here that break. This change constrains both of them to debug builds (via DEBUG() or #ifndef NDEBUG). Reviewers: bkramer, t.p.northover Subscribers: mehdi_amini, vkalintiris Differential Revision: https://reviews.llvm.org/D26421 llvm-svn: 286300
* [ThinLTO] Prevent exporting of locals used/defined in module level asmTeresa Johnson2016-11-084-13/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch uses the same approach added for inline asm in r285513 to similarly prevent promotion/renaming of locals used or defined in module level asm. All static global values defined in normal IR and used in module level asm should be included on either the llvm.used or llvm.compiler.used global. The former were already being flagged as NoRename in the summary, and I've simply added llvm.compiler.used values to this handling. Module level asm may also contain defs of values. We need to prevent export of any refs to local values defined in module level asm (e.g. a ref in normal IR), since that also requires renaming/promotion of the local. To do that, the summary index builder looks at all values in the module level asm string that are not marked Weak or Global, which is exactly the set of locals that are defined. A summary is created for each of these local defs and flagged as NoRename. This required adding handling to the BitcodeWriter to look at GV declarations to see if they have a summary (rather than skipping them all). Finally, added an assert to IRObjectFile::CollectAsmUndefinedRefs to ensure that an MCAsmParser is available, otherwise the module asm parse would silently fail. Initialized the asm parser in the opt tool for use in testing this fix. Fixes PR30610. Reviewers: mehdi_amini Subscribers: johanengelen, krasin, llvm-commits Differential Revision: https://reviews.llvm.org/D26146 llvm-svn: 286297
* [asan] Speed up compilation of large C++ stringmaps (tons of allocas) with ASanKuba Brecka2016-11-081-6/+12
| | | | | | | | This addresses PR30746, <https://llvm.org/bugs/show_bug.cgi?id=30746>. The ASan pass iterates over entry-block instructions and checks each alloca whether it's in NonInstrumentedStaticAllocaVec, which is apparently slow. This patch gathers the instructions to move during visitAllocaInst. Differential Revision: https://reviews.llvm.org/D26380 llvm-svn: 286296
* [BasicAA] Teach BasicAA to handle the inaccessiblememonly and ↵Andrew Kaylor2016-11-082-2/+7
| | | | | | | | inaccessiblemem_or_argmemonly attributes Differential Revision: https://reviews.llvm.org/D26382 llvm-svn: 286294
* AArch64DeadRegisterDefinitionsPass: Fix Changed flagMatthias Braun2016-11-081-1/+0
| | | | | | Fix a bug in the calculation of the changed flag introduced in r285488. llvm-svn: 286293
* [TBAA] Drop support for "old style" scalar TBAA tagsSanjoy Das2016-11-082-57/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: We've had support for auto upgrading old style scalar TBAA access metadata tags into the "new" struct path aware TBAA metadata for 3 years now. The only way to actually generate old style TBAA was explicitly through the IRBuilder API. I think this is a good time for dropping support for old style scalar TBAA. I'm not removing support for textual or bitcode upgrade -- if you have IR with the old style scalar TBAA tags that go through the AsmParser orf the bitcode parser before LLVM sees them, they will keep working as usual. Note: %val = load i32, i32* %ptr, !tbaa !N !N = < scalar tbaa node > is equivalent to %val = load i32, i32* %ptr, !tbaa !M !N = < scalar tbaa node > !M = !{!N, !N, 0} Reviewers: manmanren, chandlerc, sunfish Subscribers: mcrosier, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D26229 llvm-svn: 286291
* GlobalISel: allow CodeGen to fallback on VReg type/class issues.Tim Northover2016-11-082-25/+38
| | | | | | | | | After instruction selection we perform some checks on each VReg just before discarding the type information. These checks were assertions before, but that breaks the fallback path so this patch moves the logic into the main flow and reports a better error on failure. llvm-svn: 286289
* [SystemZ] Add missing FP extension instructionsUlrich Weigand2016-11-084-18/+42
| | | | | | | | This completes assembler / disassembler support for all BFP instructions provided by the floating-point extensions facility. The instructions added here are not currently used for codegen. llvm-svn: 286285
* [SystemZ] Add program mask and addressing mode instructionsUlrich Weigand2016-11-085-11/+109
| | | | | | | | | Add several instructions that operate on the program mask or the addressing mode. These are not really needed for code generation under Linux, but are provided for completeness for the assembler/disassembler. llvm-svn: 286284
* [SystemZ] Model access registers as LLVM registersUlrich Weigand2016-11-0817-102/+126
| | | | | | | | | | | | | Add the 16 access registers as LLVM registers. This allows removing a lot of special cases in the assembler and disassembler where we were handling access registers; this can all just use the generic register code now. Also add a bunch of instructions to operate on access registers, for assembler/disassembler use only. No change in code generation intended. llvm-svn: 286283
* [LoopDistribute] Preserve GlobalsAA also in the new Pass Manager.Davide Italiano2016-11-081-0/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D26408 llvm-svn: 286280
* Don't store Twine in a local variable.Eli Friedman2016-11-081-2/+1
| | | | | | Fixes post-commit review comment from r286177. llvm-svn: 286275
* [WebAssembly] Convert stackified IMPLICIT_DEF into constant 0.Dan Gohman2016-11-081-0/+37
| | | | | | | | | | Since IMPLIFIT_DEF instructions are omitted in the output, when the output of an IMPLICIT_DEF instruction is stackified, the resulting register lacks an explicit push, leading to a push/pop mismatch. Fix this by converting such IMPLICIT_DEFs into CONST_I32 0 instructions so that they have explicit pushes. llvm-svn: 286274
* [GlobalISel] Dump all instructions inserted by selector.Ahmed Bougacha2016-11-081-3/+9
| | | | | | This is helpful when multiple instructions are inserted. llvm-svn: 286273
* [GlobalISel] Permit select() to erase.Ahmed Bougacha2016-11-081-5/+22
| | | | | | | | | | | Erasing reverse_iterators is problematic; iterate manually. While there, keep track of the range of inserted instructions. It can miss instructions inserted elsewhere, but those are harder to track. Differential Revision: http://reviews.llvm.org/D22924 llvm-svn: 286272
* [LibcallsShrinkWrap] This pass doesn't preserve the CFG.Davide Italiano2016-11-081-2/+5
| | | | | | | | | | For example, it invalidates the domtree, causing assertions in later passes which need dominator infos. Make it preserve GlobalsAA, as suggested by Eli. Differential Revision: https://reviews.llvm.org/D26381 llvm-svn: 286271
* Fix typo in comment. NFC.Chad Rosier2016-11-081-2/+2
| | | | llvm-svn: 286270
* [SystemZ] Always use semantic instruction classesUlrich Weigand2016-11-083-96/+190
| | | | | | | | | | Define a couple of additional semantic classes and use them throughout the .td files to make them more consistent and more easily readable. No functional change. llvm-svn: 286268
* [SystemZ] Refactor InstRR* instruction format patternsUlrich Weigand2016-11-083-227/+260
| | | | | | | | | | | | | | | This changes the InstRR (and related) patterns to no longer automatically add an "r" at the end of the mnemonic. This makes the .td files more obviously understandable, and also allows using the patterns for those few instructions that do not follow the *r scheme. Also add some more sub-formats of the RRF format class, to match operand names and sequence from the PoP better. No functional change. llvm-svn: 286267
* [SystemZ] Rename some Inst* instruction format classesUlrich Weigand2016-11-082-96/+96
| | | | | | | | | | | Now that we've added instruction format subclasses like InstRIb, it makes sense to rename the old InstRI to InstRIa. Similar for InstRX, InstRXY, InstRS, InstRSY, and InstSS. No functional change. llvm-svn: 286266
* [MC][AArch64] Cleanup end-of-line parsing in AArch64 AsmParser.Nirav Dave2016-11-081-222/+136
| | | | | | | | | | Reviewers: t.p.northover, rengolin Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D26309 llvm-svn: 286265
* [SystemZ] Refactor branch and conditional instruction patternsUlrich Weigand2016-11-086-615/+978
| | | | | | | | | | | | | | | | | Rework patterns for branches, call & return instructions, compare-and-branch, compare-and-trap, and conditional move instructions. In particular, simplify creation of patterns for the extended opcodes of instructions that take a CC mask. Also, use semantical instruction classes for all the instructions instead of open-coding them in SystemZInstrInfo.td. Adds a couple of the basic branch instructions (that are unused for codegen) for the assembler/disassembler. llvm-svn: 286263
* NFC small changes in MemDepPiotr Padlewski2016-11-081-3/+3
| | | | llvm-svn: 286260
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