diff options
| author | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2016-11-09 12:47:57 +0000 |
|---|---|---|
| committer | Jonas Paulsson <paulsson@linux.vnet.ibm.com> | 2016-11-09 12:47:57 +0000 |
| commit | e127fe7083895d8ec5a44bbfd0b6ee75769ca45c (patch) | |
| tree | 8f47bf1dff710cb034d99faa75a360fc40d29aad /llvm/lib | |
| parent | c207bec388e36229cb25865c0e8326b80736e823 (diff) | |
| download | bcm5719-llvm-e127fe7083895d8ec5a44bbfd0b6ee75769ca45c.tar.gz bcm5719-llvm-e127fe7083895d8ec5a44bbfd0b6ee75769ca45c.zip | |
[SystemZ] A few fixes in scheduler files.
Review: U Weigand
llvm-svn: 286362
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZScheduleZ196.td | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td | 8 |
3 files changed, 11 insertions, 11 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index d5b2c127995..7bf15b40431 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -527,7 +527,7 @@ def : InstRW<[FXa, FXb, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>; def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>; // Load address extended -def : InstRW<[LSU, FXa], (instregex "LAE(Y)?$")>; +def : InstRW<[LSU, FXa, Lat5, BeginGroup], (instregex "LAE(Y)?$")>; // Load/store access multiple (not modeled precisely) def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>; @@ -546,10 +546,10 @@ def : InstRW<[LSU, EndGroup], (instregex "SPM$")>; def : InstRW<[FXa, FXa, FXb, Lat5, GroupAlone], (instregex "BAL(R)?$")>; // Test addressing mode -def : InstRW<[FXb, EndGroup], (instregex "TAM$")>; +def : InstRW<[FXb], (instregex "TAM$")>; // Set addressing mode -def : InstRW<[FXb, FXb, Lat2, EndGroup], (instregex "SAM(24|31|64)$")>; +def : InstRW<[FXb, Lat2, EndGroup], (instregex "SAM(24|31|64)$")>; // Branch (and save) and set mode. def : InstRW<[FXa, FXb, Lat2, GroupAlone], (instregex "BSM$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index c4c377e0702..06575059328 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -504,7 +504,7 @@ def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>; def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>; // Load address extended -def : InstRW<[LSU, FXU], (instregex "LAE(Y)?$")>; +def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>; // Load/store access multiple (not modeled precisely) def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>; @@ -523,14 +523,14 @@ def : InstRW<[LSU, EndGroup], (instregex "SPM$")>; def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>; // Test addressing mode -def : InstRW<[FXU, EndGroup], (instregex "TAM$")>; +def : InstRW<[FXU], (instregex "TAM$")>; // Set addressing mode def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>; // Branch (and save) and set mode. -def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "BSM$")>; -def : InstRW<[FXU, FXU, LSU, Lat5, GroupAlone], (instregex "BASSM$")>; +def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>; +def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>; //===----------------------------------------------------------------------===// // Miscellaneous Instructions. diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index 08a49b9e479..e302d4606b4 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -506,7 +506,7 @@ def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>; def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>; // Load address extended -def : InstRW<[LSU, FXU], (instregex "LAE(Y)?$")>; +def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>; // Load/store access multiple (not modeled precisely) def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>; @@ -525,14 +525,14 @@ def : InstRW<[LSU, EndGroup], (instregex "SPM$")>; def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>; // Test addressing mode -def : InstRW<[FXU, EndGroup], (instregex "TAM$")>; +def : InstRW<[FXU], (instregex "TAM$")>; // Set addressing mode def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>; // Branch (and save) and set mode. -def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "BSM$")>; -def : InstRW<[FXU, FXU, LSU, Lat5, GroupAlone], (instregex "BASSM$")>; +def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>; +def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>; //===----------------------------------------------------------------------===// // Transactional execution |
