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* [Hexagon] Adding encoding bits for add opcode.Colin LeMahieu2014-10-2210-177/+225
| | | | | | | | | Adding llvm-mc tests. Removing unit tests. http://reviews.llvm.org/D5624 llvm-svn: 220427
* [AArch64] Add support for the .inst directive.Chad Rosier2014-10-225-0/+137
| | | | | | | | | | This has been implement using the MCTargetStreamer interface as is done in the ARM, Mips and PPC backends. Phabricator: http://reviews.llvm.org/D5891 PR20964 llvm-svn: 220422
* Strength reduce constant-sized vectors into arrays. No functionality change.Benjamin Kramer2014-10-222-10/+8
| | | | llvm-svn: 220412
* LoopVectorize: Simplify code. No functionality change.Benjamin Kramer2014-10-221-19/+7
| | | | llvm-svn: 220405
* Shorten auto iterators for function basic blocks.Diego Novillo2014-10-221-37/+36
| | | | | | | | Use consistent naming for basic block instances. No functional changes. llvm-svn: 220404
* Fix VS2012 build; C++11 type aliases are not supported.Hans Wennborg2014-10-221-1/+2
| | | | llvm-svn: 220399
* Ammending 220393 - Removing unused decoding tables.Colin LeMahieu2014-10-221-18/+0
| | | | llvm-svn: 220397
* Ammending 220393 - Removing unused functions.Colin LeMahieu2014-10-221-33/+0
| | | | llvm-svn: 220396
* [PATCH] Support select-cc for VSFRC when VSX is enabledBill Schmidt2014-10-223-5/+36
| | | | | | | | | | | | | | A previous patch enabled SELECT_VSRC and SELECT_CC_VSRC for VSX to handle <2 x double> cases. This patch adds SELECT_VSFRC and SELECT_CC_VSFRC to allow use of all 64 vector-scalar registers for the f64 type when VSX is enabled. The changes are analogous to those in the previous patch. I've added a new variant to vsx.ll to test the code generation. (I also cleaned up a little formatting in PPCInstrVSX.td from the previous patch.) llvm-svn: 220395
* Use auto iteration in lib/Transforms/Scalar/SampleProfile.cpp. No functional ↵Diego Novillo2014-10-221-18/+15
| | | | | | changes. llvm-svn: 220394
* [Hexagon] Adding basic disassembler.Colin LeMahieu2014-10-2210-44/+238
| | | | | | | Marking all instructions as CodeGenOnly since encoding bits are not set yet. http://reviews.llvm.org/D5829?vs=on&id=15023&whitespace=ignore-all#toc llvm-svn: 220393
* Preserving 'nonnull' metadata in SimplifyCFGPhilip Reames2014-10-221-1/+4
| | | | | | | | | | When we hoist two loads above an if, we can preserve the nonnull metadata. We could also do the same for sinking them, but we appear to not handle metadata at all in that case. Thanks to Hal for the review. Differential Revision: http://reviews.llvm.org/D5910 llvm-svn: 220392
* Shrinkify libcalls: use float versions of double libm functions with ↵Sanjay Patel2014-10-222-10/+24
| | | | | | | | | | | | | | | | | | | | | | | | fast-math (bug 17850) When a call to a double-precision libm function has fast-math semantics (via function attribute for now because there is no IR-level FMF on calls), we can avoid fpext/fptrunc operations and use the float version of the call if the input and output are both float. We already do this optimization using a command-line option; this patch just adds the ability for fast-math to use the existing functionality. I moved the cl::opt from InstructionCombining into SimplifyLibCalls because it's only ever used internally to that class. Modified the existing test cases to use the unsafe-fp-math attribute rather than repeating all tests. This patch should solve: http://llvm.org/bugs/show_bug.cgi?id=17850 Differential Revision: http://reviews.llvm.org/D5893 llvm-svn: 220390
* Change error to warning when a profile cannot be found.Diego Novillo2014-10-221-1/+3
| | | | | | | | When the profile for a function cannot be applied, we use to emit an error. This seems extreme. The compiler can continue, it's just that the optimization opportunities won't include profile information. llvm-svn: 220386
* [PowerPC] Support select-cc for VSXBill Schmidt2014-10-223-3/+40
| | | | | | | | | | | | | | | | | | | | | | | | | The tests test/CodeGen/Generic/select-cc.ll and test/CodeGen/PowerPC/select-cc.ll both fail with VSX enabled. The problem is that the lowering logic for the SELECT and SELECT_CC operations doesn't currently support the VSX registers. This patch fixes that. In lib/Target/PowerPC/PPCInstrInfo.td, we have pseudos to handle this for other register classes. Similar pseudos are added in PPCInstrVSX.td (they must be there, because the "vsrc" register class definition appears there) for the VSRC register class. The SELECT_VSRC pseudo is then used in pattern matching for SELECT_CC. The rest of the patch just adds logic for SELECT_VSRC wherever similar logic appears for SELECT_VRRC. There are no new test cases because the existing tests above test this, along with a variant in test/CodeGen/PowerPC/vsx.ll. After discussion with Hal, a future patch will add similar _VSFRC variants to override f64 type handling (currently using F8RC). llvm-svn: 220385
* Support using sample profiles with partial debug info.Diego Novillo2014-10-221-12/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When using a profile, we used to require the use -gmlt so that we could get access to the line locations. This is used to match line numbers in the input profile to the line numbers in the function's IR. But this is actually not necessary. The driver can provide source location tracking without the emission of debug information. In these cases, the annotation 'llvm.dbg.cu' is missing from the IR, but the actual line location annotations are still present. This patch adds a new way of looking for the start of the current function. Instead of looking through the compile units in llvm.dbg.cu, we can walk up the scope for the first instruction in the function with a debug loc. If that describes the function, we use it. Otherwise, we keep looking until we find one. If no such instruction is found, we then give up and produce an error. Reviewers: echristo, dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5887 llvm-svn: 220382
* [AArch64] Cleanup A57PBQPConstraintsArnaud A. de Grandmaison2014-10-223-48/+50
| | | | | | And add a long awaited testcase. llvm-svn: 220381
* [InstSimplify] Support constant folding to vector of pointersBruno Cardoso Lopes2014-10-221-2/+12
| | | | | | | | | | | | | | | | | | | ConstantFolding crashes when trying to InstSimplify the following load: @a = private unnamed_addr constant %mst { i8* inttoptr (i64 -1 to i8*), i8* inttoptr (i64 -1 to i8*) }, align 8 %x = load <2 x i8*>* bitcast (%mst* @a to <2 x i8*>*), align 8 This patch fix this by adding support to this type of folding: %x = load <2 x i8*>* bitcast (%mst* @a to <2 x i8*>*), align 8 ==> gets folded to: %x = <2 x i8*> <i8* inttoptr (i64 -1 to i8*), i8* inttoptr (i64 -1 to i8*)> llvm-svn: 220380
* [Thumb/Thumb2] Implement restrictions on SP in register list on LDM, STM ↵Jyoti Allur2014-10-221-2/+23
| | | | | | variants in thumb mode llvm-svn: 220379
* Fix typoMatt Arsenault2014-10-221-1/+1
| | | | llvm-svn: 220353
* [msan] Handle param-tls overflow.Evgeniy Stepanov2014-10-221-14/+34
| | | | | | | | ParamTLS (shadow for function arguments) is of limited size. This change makes all arguments that do not fit unpoisoned, and avoids writing past the end of a TLS buffer. llvm-svn: 220351
* Revert "Teach the load analysis to allow finding available values which ↵Hans Wennborg2014-10-214-39/+9
| | | | | | | | require" (r220277) This seems to have caused PR21330. llvm-svn: 220349
* [MCJIT] Defer application of AArch64 MachO GOT relocations until resolve time.Lang Hames2014-10-211-5/+5
| | | | | | | | | | On AArch64, GOT references are page relative (ADRP + LDR), so they can't be applied until we know exactly where, within a page, the GOT entry will be in the target address space. Fixes <rdar://problem/18693976>. llvm-svn: 220347
* LTO: respect command-line options that disable vectorization.JF Bastien2014-10-211-2/+4
| | | | | | | | | | | | Summary: Patches 202051 and 208013 added calls to LTO's PassManager which unconditionally add LoopVectorizePass and SLPVectorizerPass instead of following the logic in PassManagerBuilder::populateModulePassManager and honoring the -vectorize-loops -run-slp-after-loop-vectorization flags. Reviewers: nadav, aschwaighofer, yijiang Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5884 llvm-svn: 220345
* Add minnum / maxnum codegenMatt Arsenault2014-10-2115-4/+202
| | | | llvm-svn: 220342
* Add minnum / maxnum intrinsicsMatt Arsenault2014-10-215-0/+105
| | | | | | | | | | | | These are named following the IEEE-754 names for these functions, rather than the libm fmin / fmax to avoid possible ambiguities. Some languages may implement something resembling fmin / fmax which return NaN if either operand is to propagate errors. These implement the IEEE-754 semantics of returning the other operand if either is a NaN representing missing data. llvm-svn: 220341
* IR: Reorder metadata bitcode serialization, NFCDuncan P. N. Exon Smith2014-10-211-12/+14
| | | | | | | | | Enumerate `MDNode`'s operands *before* the node itself, so that the reader requires less RAUW. Although this will cause different code paths to be hit in the reader, this should effectively be no functionality change. llvm-svn: 220340
* R600/SI: Add missing parameter to div_fmas intrinsicMatt Arsenault2014-10-211-0/+2
| | | | llvm-svn: 220338
* IR: Remove dead code in metadata bitcode writing, NFCDuncan P. N. Exon Smith2014-10-213-16/+12
| | | | | | | No one cares how many uses each metadata value has, so don't bother counting. llvm-svn: 220337
* Pacify bots and simplify r220321Arnaud A. de Grandmaison2014-10-211-1/+1
| | | | llvm-svn: 220335
* R600: Use default GlobalDirectiveMatt Arsenault2014-10-211-1/+0
| | | | | | | The overridden one wasn't inserting a space, so you would end up with .globalfoo llvm-svn: 220329
* Teach combineMetadata how to merge 'nonnull' metadata.Philip Reames2014-10-211-0/+4
| | | | | | combineMetadata is used when merging two instructions into one. This change teaches it how to merge 'nonnull' - i.e. only preserve it on the new instruction if it's set on both sources. This isn't actually used yet since I haven't adjusted any of the call sites to pass in nonnull as a 'known metadata'. llvm-svn: 220325
* Preserve 'nonnull' when changing type of the load.Philip Reames2014-10-211-0/+1
| | | | | | | | When changing the type of a load in Chandler's recent InstCombine changes, we can preserve the new 'nonnull' metadata. I considered adding an assert since 'nonnull' is only valid on pointer types, but casting a pointer to a non-pointer would involve more than a bitcast anyways. If someone extends this transform to handle more than bitcasts, the verifier will report the malformed IR, so a separate assertion isn't needed. Also, the fpmath flags would have the same problem. llvm-svn: 220324
* Extend the verifier to check usage of 'nonnull' metadata.Philip Reames2014-10-211-0/+8
| | | | | | The recently added !nonnull metadata is only valid on loads of pointer type. llvm-svn: 220323
* [PBQP] Teach PassConfig to tell if the default register allocator is used.Arnaud A. de Grandmaison2014-10-213-17/+8
| | | | | | | | This enables targets to adapt their pass pipeline to the register allocator in use. For example, with the AArch64 backend, using PBQP with the cortex-a57, the FPLoadBalancing pass is no longer necessary. llvm-svn: 220321
* InstCombine: Simplify FoldICmpCstShrCstDavid Majnemer2014-10-211-48/+16
| | | | | | | | | This function was complicated by the fact that it tried to perform canonicalizations that were already preformed by InstSimplify. Remove this extra code and move the tests over to InstSimplify. Add asserts to make sure our preconditions hold before we make any assumptions. llvm-svn: 220314
* Drop support for an old version of ld64 (from darwin 9).Rafael Espindola2014-10-214-17/+0
| | | | llvm-svn: 220310
* remove function names from comments; NFCSanjay Patel2014-10-211-2/+2
| | | | llvm-svn: 220309
* R600/SI: Add pattern for bswapMatt Arsenault2014-10-213-0/+19
| | | | llvm-svn: 220304
* [PBQP] Fix coalescing benefitsArnaud A. de Grandmaison2014-10-211-2/+2
| | | | | | As coalescing registers is a benefit, the cost should be improved (i.e. made smaller) when coalescing is possible. llvm-svn: 220302
* X86AsmInstrumentation.cpp: Dissolve initializer-ranged-for. MSC17 disliked it.NAKAMURA Takumi2014-10-211-3/+3
| | | | llvm-svn: 220301
* Test commitColin LeMahieu2014-10-211-1/+1
| | | | | | Fixing brief comment. llvm-svn: 220299
* [PowerPC] Avoid VSX FMA mutate when killed product reg = addend regBill Schmidt2014-10-211-0/+6
| | | | | | | | | | | | | | | | | | | | | With VSX enabled, test/CodeGen/PowerPC/recipest.ll exposes a bug in the FMA mutation pass. If we have a situation where a killed product register is the same register as the FMA target, such as: %vreg5<def,tied1> = XSNMSUBADP %vreg5<tied0>, %vreg11, %vreg5, %RM<imp-use>; VSFRC:%vreg5 F8RC:%vreg11 then the substitution makes no sense. We end up getting a crash when we try to extend the interval associated with the killed product register, as there is already a live range for %vreg5 there. This patch just disables the mutation under those circumstances. Since recipest.ll generates different code with VMX enabled, I've modified that test to use -mattr=-vsx. I've borrowed the code from that test that exposed the bug and placed it in fma-mutate.ll, where it tests several mutation opportunities including the "bad" one. llvm-svn: 220290
* [ARM] NEON 32-bit scalar moves are also available in VFPv2Oliver Stannard2014-10-211-2/+3
| | | | | | | | | | | The 32-bit variants of the NEON scalar<->GPR move instructions are also available in VFPv2. The 8- and 16-bit variants do require NEON. Note that the checks in the test file are all -DAG because they are checking a mixture of stdout and stderr, and the ordering is not guaranteed. llvm-svn: 220288
* [asan-asm-instrumentation] Fixed memory accesses with rbp as a base or an ↵Yuri Gorshenin2014-10-211-63/+121
| | | | | | | | | | | | | | index register. Summary: Fixed memory accesses with rbp as a base or an index register. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5819 llvm-svn: 220283
* [Thumb2] LDRS?[BH] cannot load to the PCOliver Stannard2014-10-211-4/+4
| | | | | | | The Thumb2 LDRS?[BH] instructions are not valid when the destination register is the PC (these encodings are used for preload hints). llvm-svn: 220278
* Teach the load analysis to allow finding available values which requireChandler Carruth2014-10-214-9/+39
| | | | | | | | | | | | | | | | | | | | inttoptr or ptrtoint cast provided there is datalayout available. Eventually, the datalayout can just be required but in practice it will always be there today. To go with the ability to expose available values requiring a ptrtoint or inttoptr cast, helpers are added to perform one of these three casts. These smarts are necessary to finish canonicalizing loads and stores to the operational type requirements without regressing fundamental combines. I've added some test cases. These should actually improve as the load combining and store combining improves, but they may fundamentally be highlighting some missing combines for select in addition to exercising the specific added logic to load analysis. llvm-svn: 220277
* [mips][microMIPS] Implement ADDU16 and SUBU16 instructionsZoran Jovanovic2014-10-212-0/+27
| | | | | | Differential Revision: http://reviews.llvm.org/D5118 llvm-svn: 220276
* [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructionsZoran Jovanovic2014-10-212-0/+34
| | | | | | Differential Revision: http://reviews.llvm.org/D5117 llvm-svn: 220275
* [mips][microMIPS] Implement microMIPS 16-bit instructions registersZoran Jovanovic2014-10-213-0/+46
| | | | | | Differential Revision: http://reviews.llvm.org/D5116 llvm-svn: 220273
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