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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-21 11:49:14 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-21 11:49:14 +0000 |
| commit | cdb8db8d3cd35111e149231cc6fb2bb7bae46cc8 (patch) | |
| tree | 51d3e176a8fc2b789c634544f7d5cc0aad6b2577 /llvm/lib | |
| parent | c0126864a0fbcd78e9dcf02faec43891691b77d4 (diff) | |
| download | bcm5719-llvm-cdb8db8d3cd35111e149231cc6fb2bb7bae46cc8.tar.gz bcm5719-llvm-cdb8db8d3cd35111e149231cc6fb2bb7bae46cc8.zip | |
[ARM] NEON 32-bit scalar moves are also available in VFPv2
The 32-bit variants of the NEON scalar<->GPR move instructions are
also available in VFPv2. The 8- and 16-bit variants do require NEON.
Note that the checks in the test file are all -DAG because they are
checking a mixture of stdout and stderr, and the ordering is not
guaranteed.
llvm-svn: 220288
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 9f11c5bfffb..a0c627c3541 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -5437,7 +5437,7 @@ def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00, IIC_VMOVSI, "vmov", "32", "$R, $V$lane", [(set GPR:$R, (extractelt (v2i32 DPR:$V), imm:$lane))]>, - Requires<[HasNEON, HasFastVGETLNi32]> { + Requires<[HasVFP2, HasFastVGETLNi32]> { let Inst{21} = lane{0}; } // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td @@ -5505,7 +5505,8 @@ def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V), (ins DPR:$src1, GPR:$R, VectorIndex32:$lane), IIC_VMOVISL, "vmov", "32", "$V$lane, $R", [(set DPR:$V, (insertelt (v2i32 DPR:$src1), - GPR:$R, imm:$lane))]> { + GPR:$R, imm:$lane))]>, + Requires<[HasVFP2]> { let Inst{21} = lane{0}; // This instruction is equivalent as // $V = INSERT_SUBREG $src1, $R, translateImmToSubIdx($imm) |
