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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-21 09:14:15 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-21 09:14:15 +0000 |
| commit | 38e6d45a463ab5bcc0cab1df88e7e6886512c206 (patch) | |
| tree | cc42dde9b770bba7093682198d22dcf0d17b8e30 /llvm/lib | |
| parent | aa72a6dd3bd1a880e30c76545cdbb8928c104cd4 (diff) | |
| download | bcm5719-llvm-38e6d45a463ab5bcc0cab1df88e7e6886512c206.tar.gz bcm5719-llvm-38e6d45a463ab5bcc0cab1df88e7e6886512c206.zip | |
[Thumb2] LDRS?[BH] cannot load to the PC
The Thumb2 LDRS?[BH] instructions are not valid when the destination
register is the PC (these encodings are used for preload hints).
llvm-svn: 220278
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrThumb2.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td index 7e5c9bcbe75..807c2524863 100644 --- a/llvm/lib/Target/ARM/ARMInstrThumb2.td +++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td @@ -1262,15 +1262,15 @@ defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, // Loads with zero extension defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, - GPR, UnOpFrag<(zextloadi16 node:$Src)>>; + GPRnopc, UnOpFrag<(zextloadi16 node:$Src)>>; defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, - GPR, UnOpFrag<(zextloadi8 node:$Src)>>; + GPRnopc, UnOpFrag<(zextloadi8 node:$Src)>>; // Loads with sign extension defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, - GPR, UnOpFrag<(sextloadi16 node:$Src)>>; + GPRnopc, UnOpFrag<(sextloadi16 node:$Src)>>; defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, - GPR, UnOpFrag<(sextloadi8 node:$Src)>>; + GPRnopc, UnOpFrag<(sextloadi8 node:$Src)>>; let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { // Load doubleword |
