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* Revert "SDAG: Update ChainNodesMatched as nodes are deleted"Justin Bogner2016-06-031-9/+4
| | | | | | | | | Seeing failures in CodeGen/Generic/icmp-illegal.ll on quite a few bots. This reverts r271706. llvm-svn: 271713
* Test commit. Removes some spaces. No functionality changed.Alina Sbirlea2016-06-031-22/+22
| | | | | | | | | | | | Summary: Test commit. Removes some spaces. No functionality changed. Reviewers: llvm-commits Differential Revision: http://reviews.llvm.org/D20972 llvm-svn: 271711
* SDAG: Update ChainNodesMatched as nodes are deletedJustin Bogner2016-06-031-4/+9
| | | | | | | Avoid relying on UB by looking into deleted nodes for a marker value. Instead, update the list of chain nodes as we go. llvm-svn: 271706
* In openFileForRead, attempt to fetch the actual name of the file on disk -- ↵Taewook Oh2016-06-032-2/+131
| | | | | | | | | | including case -- so that clang can later warn about non-portable #include and #import directives. Differential Revision: http://reviews.llvm.org/D19842 Patch by Eric Niebler llvm-svn: 271704
* [WebAssembly] Emit type signatures for declared functionsDerek Schuff2016-06-033-10/+56
| | | | | | | | | | | | | | | | | | | | | Under emscripten, C code can take the address of a function implemented in Javascript (which is exposed via an import in wasm). Because imports do not have linear memory address in wasm, we need to generate a thunk to be the target of the indirect call; it call the import directly. To make this possible, LLVM needs to emit the type signatures for these functions, because they may not be called directly or referred to other than where the address is taken. This uses s new .s directive (.functype) which specifies the signature. Differential Revision: http://reviews.llvm.org/D20891 Re-apply r271599 but instead of bailing with an error when a declared function has multiple returns, replace it with a pointer argument. Also add the test case I forgot to 'git add' last time around. llvm-svn: 271703
* SDAG: Replace some unreachable code with an assert. NFCJustin Bogner2016-06-031-6/+3
| | | | | | | The current node shouldn't be (and isn't) removed partway through selection. llvm-svn: 271699
* [libfuzzer] splitting fuzzer.testMike Aizatsky2016-06-0311-97/+99
| | | | llvm-svn: 271697
* [codeview] Add basic record type translationReid Kleckner2016-06-033-9/+229
| | | | | | | | | | | This only translates data members for now. Translating overloaded methods is complicated, so I stopped short of doing that. Reviewers: aaboud Differential Revision: http://reviews.llvm.org/D20924 llvm-svn: 271680
* Code size optimisation: do not inline memcpy if this expansion resultsSjoerd Meijer2016-06-031-0/+6
| | | | | | | | in more instructions than the libary call. Differential Revision: http://reviews.llvm.org/D20958 llvm-svn: 271678
* [AArch64] Spot SBFX-compatbile code expressed with sign_extend_inreg.Chad Rosier2016-06-031-0/+37
| | | | | | | | | | We were assuming all SBFX-like operations would have the shl/asr form, but often when the field being extracted is an i8 or i16, we end up with a SIGN_EXTEND_INREG acting on a shift instead. This is a port of r213754 from ARM to AArch64. llvm-svn: 271677
* [InstCombine] look through bitcasts to find selectsSanjay Patel2016-06-031-18/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was concern that creating bitcasts for the simpler potential select pattern: define <2 x i64> @vecBitcastOp1(<4 x i1> %cmp, <2 x i64> %a) { %a2 = add <2 x i64> %a, %a %sext = sext <4 x i1> %cmp to <4 x i32> %bc = bitcast <4 x i32> %sext to <2 x i64> %and = and <2 x i64> %a2, %bc ret <2 x i64> %and } might lead to worse code for some targets, so this patch is matching the larger patterns seen in the test cases. The motivating example for this patch is this IR produced via SSE intrinsics in C: define <2 x i64> @gibson(<2 x i64> %a, <2 x i64> %b) { %t0 = bitcast <2 x i64> %a to <4 x i32> %t1 = bitcast <2 x i64> %b to <4 x i32> %cmp = icmp sgt <4 x i32> %t0, %t1 %sext = sext <4 x i1> %cmp to <4 x i32> %t2 = bitcast <4 x i32> %sext to <2 x i64> %and = and <2 x i64> %t2, %a %neg = xor <4 x i32> %sext, <i32 -1, i32 -1, i32 -1, i32 -1> %neg2 = bitcast <4 x i32> %neg to <2 x i64> %and2 = and <2 x i64> %neg2, %b %or = or <2 x i64> %and, %and2 ret <2 x i64> %or } For an AVX target, this is currently: vpcmpgtd %xmm1, %xmm0, %xmm2 vpand %xmm0, %xmm2, %xmm0 vpandn %xmm1, %xmm2, %xmm1 vpor %xmm1, %xmm0, %xmm0 retq With this patch, it becomes: vpmaxsd %xmm1, %xmm0, %xmm0 Differential Revision: http://reviews.llvm.org/D20774 llvm-svn: 271676
* [test/AMDGPU] Square-braced-syntax for registers: add macro test/example.Artem Tamazov2016-06-031-19/+45
| | | | | | | | | | Test added as per discussion in http://reviews.llvm.org/D20588. The macro is just a demonstration, useless in practice. Coding style fixes. Differential Revision: http://reviews.llvm.org/D20797 llvm-svn: 271675
* RAS extensions are part of ARMv8.2-A. This change enables them by introducing aSjoerd Meijer2016-06-0313-24/+131
| | | | | | | | | | new instruction to ARM and AArch64 targets and several system registers. Patch by: Roger Ferrer Ibanez and Oliver Stannard Differential Revision: http://reviews.llvm.org/D20282 llvm-svn: 271670
* Adding reserve and capacity methods to FoldingSetBen Craig2016-06-031-5/+20
| | | | | | http://reviews.llvm.org/D20930 llvm-svn: 271669
* ARM target does not use printAliasInstr machinery whichSjoerd Meijer2016-06-037-137/+100
| | | | | | | | | | | | | | | | | | forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
* [AMDGPU] Assembler: More tests for SDWA instructions. Fix for SDWA float ↵Sam Kolton2016-06-032-16/+23
| | | | | | | | | | | | | | modifiers. Summary: Depends on D20625 Reviewers: tstellarAMD, vpykhtin, artem.tamazov Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D20674 llvm-svn: 271662
* [mips] EABI CodeGen is completely untested and seems to have bitrotted. ↵Daniel Sanders2016-06-037-69/+3
| | | | | | | | | | | | | | | | | | Remove it. Summary: There are no tests*, no EABI buildbots, and simple test cases do not work. * There is a single MIPS16 test using a mips*-gnueabi triple but this test doesn't test EABI and the triple doesn't cause EABI to be used. Reviewers: sdardis Subscribers: tberghammer, danalbert, srhines, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20906 llvm-svn: 271658
* [AMDGPU] Assembler: Custom converters for SDWA instructions. Support for ↵Sam Kolton2016-06-032-62/+162
| | | | | | | | | | | | | | | | _dpp and _sdwa suffixes in mnemonics. Summary: Added custom converters for SDWA instruction to support optional operands and modifiers. Support for _dpp and _sdwa suffixes that allows to force DPP or SDWA encoding for instructions. Reviewers: tstellarAMD, vpykhtin, artem.tamazov Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D20625 llvm-svn: 271655
* Remove bogus initialization of the PPC and Hexagon SelectionDAGISelChandler Carruth2016-06-032-37/+2
| | | | | | | | | | | | | | | | | subclasses. These are not passes proper. We don't support registering them, they can't be constructed with default arguments, and the ID is actually in a base class. Only these two targets even had any boiler plate to try to do this, and it had to be munged out of the INITIALIZE_PASS macros to work. What's worse, the boiler plate has rotted and the "name" of the pass is actually the description string now!!! =/ All of this is completely unnecessary. No other target bothers, and nothing breaks if you don't initialize them because CodeGen has an entirely separate initialization path that is somewhat more durable than relying on the implicit initialization the way the 'opt' tool does for registered passes. llvm-svn: 271650
* Use the standard INITIALIZE_PASS macro rather than hand rolling a (notChandler Carruth2016-06-031-9/+2
| | | | | | entirely correct) version of its contents. llvm-svn: 271649
* [mips] Implement 'la' macro in PIC mode for O32.Daniel Sanders2016-06-034-35/+83
| | | | | | | | | | | | | | | | Summary: N32 support will follow in a later patch since the symbol version of 'la' incorrectly believes N32 to have 64-bit pointers and rejects it early. This fixes the three incorrectly expanded 'la' macros found in bionic. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20820 llvm-svn: 271644
* [X86][XOP] Support for VPERMIL2PD/VPERMIL2PS 2-input shuffle instructionsSimon Pilgrim2016-06-036-17/+74
| | | | | | | | | | | | This patch begins adding support for lowering to the XOP VPERMIL2PD/VPERMIL2PS shuffle instructions - adding the X86ISD::VPERMIL2 opcode and cleaning up the usage. The internal llvm intrinsics were assuming the shuffle mask operand was the same type as the float/double input operands (I guess to simplify the intrinsic definitions in X86InstrXOP.td to a single value type). These needed changing to integer types (matching the clang builtin and the AMD intrinsics definitions), an auto upgrade path is added to convert old calls. Mask decoding/target shuffle support will be added in future patches. Differential Revision: http://reviews.llvm.org/D20049 llvm-svn: 271633
* [X86] Fix some isel patterns to remove an operand from some multiclasses. NFCCraig Topper2016-06-031-65/+64
| | | | llvm-svn: 271631
* [pdb] Print out file names instead of file offsets.Zachary Turner2016-06-033-8/+44
| | | | | | | | | | | | When printing line information and file checksums, we were printing the file offset field from the struct header. This teaches llvm-pdbdump how to turn those numbers into the filename. In the case of file checksums, this is done by looking in the global string table. In the case of line contributions, this is done by indexing into the file names buffer of the DBI stream. Why they use a different technique I don't know. llvm-svn: 271630
* [AVX512] Ensure EVEX vpshufd, vpshuflw, and vpshufhw have isel priority over ↵Craig Topper2016-06-031-6/+8
| | | | | | the VEX encoded ones. llvm-svn: 271629
* [AVX512] Fix shuffle comment printing for EVEX encoded PSHUFD, PSHUFHW, and ↵Craig Topper2016-06-031-29/+17
| | | | | | PSHUFLW. llvm-svn: 271628
* [X86] Simplify a multiclass to remove a parameter. NFCCraig Topper2016-06-031-31/+30
| | | | llvm-svn: 271627
* [X86] Remove unnecessary pattern predicates from the vector bit cast ↵Craig Topper2016-06-032-100/+94
| | | | | | patterns. The types have to be legal and there are no alternative patterns. Saves almost 200 bytes in isel table. llvm-svn: 271625
* [X86] Cleanup formatting a bit to align similar parts of adjacent lines.Craig Topper2016-06-031-26/+26
| | | | llvm-svn: 271624
* [X86] Remove redundant bitcast patterns for 128/256-bit vectors. These only ↵Craig Topper2016-06-031-64/+0
| | | | | | differ from the SSE/AVX versions by the register class, but register class has no bearing on isel. llvm-svn: 271623
* [pdb] Dump file checksums from pdb codeview line info.Zachary Turner2016-06-032-5/+21
| | | | llvm-svn: 271622
* [codeview] Dump line number and column information.Zachary Turner2016-06-035-17/+109
| | | | | | | | | | | | | | | | | | | | | | | | | To facilitate this, a couple of changes had to be made: 1. `ModuleSubstream` got moved from `DebugInfo/PDB` to `DebugInfo/CodeView`, and various codeview related types are defined there. It turns out `DebugInfo/CodeView/Line.h` already defines many of these structures, but this is really old code that is not endian aware, doesn't interact well with `StreamInterface` and not very helpful for getting stuff out of a PDB. Eventually we should migrate the old readobj `COFFDumper` code to these new structures, or at least merge their functionality somehow. 2. A `ModuleSubstream` visitor is introduced. Depending on where your module substream array comes from, different subsets of record types can be expected. We are already hand parsing these substream arrays in many places especially in `COFFDumper.cpp`. In the future we can migrate these paths to the visitor as well, which should reduce a lot of code in `COFFDumper.cpp`. Differential Revision: http://reviews.llvm.org/D20936 Reviewed By: ruiu, majnemer llvm-svn: 271621
* [esan|cfrag] Instrument GEP instr for struct field access.Qin Zhao2016-06-031-0/+61
| | | | | | | | | | | | | | | | | Summary: Instrument GEP instruction for counting the number of struct field address calculation to approximate the number of struct field accesses. Adds test struct_field_count_basic.ll to test the struct field instrumentation. Reviewers: bruening, aizatsky Subscribers: junbuml, zhaoqin, llvm-commits, eugenis, vitalybuka, kcc, bruening Differential Revision: http://reviews.llvm.org/D20892 llvm-svn: 271619
* [LoopUnroll] Set correct thresholds for new recently enabled unrolling ↵Michael Zolotukhin2016-06-031-2/+2
| | | | | | | | | | | heuristic. In r270478, where I enabled the new heuristic I posted testing results, which I got when explicitly passed the thresholds values via CL options. However, setting the CL options init-values is not enough to change the default values of thresholds, so I'm changing them in another place now. llvm-svn: 271615
* [TailRecursionElimination] Refactor/cleanup.Davide Italiano2016-06-021-150/+121
| | | | | | | | | In preparation for porting to the new PM. Patch by Jake VanAdrighem! (review mainly by me/Justin) Differential Revision: http://reviews.llvm.org/D20610 llvm-svn: 271607
* Revert "[WebAssembly] Emit type signatures for declared functions"Derek Schuff2016-06-023-50/+10
| | | | | | | | This reverts r271599, it broke the integration tests. More places than I expected had nontrival return types in imports, or else the check was wrong. llvm-svn: 271606
* [obj2yaml] [yaml2obj] Support for MachO nlist and string tableChris Bieneman2016-06-021-0/+11
| | | | | | This commit adds round tripping for MachO symbol data. Symbols are entries in the name list, that contain offsets into the string table which is at the end of the __LINKEDIT segment. llvm-svn: 271604
* [PM] Schedule InstSimplify after late LICM run, to clean up LCSSA nodes.Manuel Jacob2016-06-021-0/+3
| | | | | | | | | | | | | | | Summary: The module pass pipeline includes a late LICM run after loop unrolling. LCSSA is implicitly run as a pass dependency of LICM. However no cleanup pass was run after this, so the LCSSA nodes ended in the optimized output. Reviewers: hfinkel, mehdi_amini Subscribers: majnemer, bruno, mzolotukhin, mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D20606 llvm-svn: 271602
* [PM] LoadCombine preserves GlobalsAA, doesn't depend on it.Davide Italiano2016-06-021-1/+0
| | | | llvm-svn: 271601
* [PM/LoadCombine] Inline getAnalysisUsage(). NFCI.Davide Italiano2016-06-021-8/+5
| | | | llvm-svn: 271600
* [WebAssembly] Emit type signatures for declared functionsDerek Schuff2016-06-023-10/+50
| | | | | | | | | | | | | | | | | Under emscripten, C code can take the address of a function implemented in Javascript (which is exposed via an import in wasm). Because imports do not have linear memory address in wasm, we need to generate a thunk to be the target of the indirect call; it call the import directly. To make this possible, LLVM needs to emit the type signatures for these functions, because they may not be called directly or referred to other than where the address is taken. This uses s new .s directive (.functype) which specifies the signature. Differential Revision: http://reviews.llvm.org/D20891 llvm-svn: 271599
* 80-column fixup after last formatting change.Eric Christopher2016-06-021-4/+8
| | | | llvm-svn: 271598
* Add comments.Rui Ueyama2016-06-021-0/+2
| | | | llvm-svn: 271597
* Fix a couple of misformatted comments spotted in post-commit review.Eric Christopher2016-06-021-8/+7
| | | | llvm-svn: 271596
* This patch is in preparation for a substantial refactoring of theEric Christopher2016-06-021-294/+304
| | | | | | | | | | | | code. To make the diffs easier to read, clang-format everything first. No functionality changed. Patch by Alina Sbirlea! http://reviews.llvm.org/D20926 llvm-svn: 271595
* fix documentation comments; NFCSanjay Patel2016-06-021-24/+1
| | | | llvm-svn: 271584
* [llvm-pdbdump] Dump CodeView line information.Zachary Turner2016-06-025-4/+80
| | | | | | | | | This first pass only splits apart the records and dumps the line info kinds and binary data. Subsequent patches will parse out the binary data into more useful information and dump it in detail. llvm-svn: 271576
* AMDGPU: Handle flat in getMemOpBaseRegImmOfsMatt Arsenault2016-06-021-0/+7
| | | | | | | It can still report the base register, and the uses give up when it fails. llvm-svn: 271575
* [ASMParser] Parse FP constants in non-C localesMeador Inge2016-06-021-2/+4
| | | | | | | | | | | This patch fixes PR25788, which allows for the parsing of floating-point constants in non-C locales. Patch by Antoine Pitrou! Differential Revision: http://reviews.llvm.org/D15375 llvm-svn: 271574
* transform obscured FP sign bit ops into a fabs/fneg using TLI hookSanjay Patel2016-06-024-28/+54
| | | | | | | | | | | | | | | | | | | This is effectively a revert of: http://reviews.llvm.org/rL249702 - [InstCombine] transform masking off of an FP sign bit into a fabs() intrinsic call (PR24886) and: http://reviews.llvm.org/rL249701 - [ValueTracking] teach computeKnownBits that a fabs() clears sign bits and a reimplementation as a DAG combine for targets that have IEEE754-compliant fabs/fneg instructions. This is intended to resolve the objections raised on the dev list: http://lists.llvm.org/pipermail/llvm-dev/2016-April/098154.html and: https://llvm.org/bugs/show_bug.cgi?id=24886#c4 In the interest of patch minimalism, I've only partly enabled AArch64. PowerPC, MIPS, x86 and others can enable later. Differential Revision: http://reviews.llvm.org/D19391 llvm-svn: 271573
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