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* Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code mod...Reid Kleckner2018-06-256-30/+121
* [X86] Sort the static memory folding tables by reg opcode. Remove the reg->me...Craig Topper2018-06-252-5419/+5328
* [X86] Allow base and index for gather instructions to appear in other order f...Craig Topper2018-06-251-0/+11
* [SelectionDAG] Remove debug locations from ConstantSD(FP)NodesVedant Kumar2018-06-251-2/+2
* Add Triple::isMIPS()/isMIPS32()/isMIPS64(). NFCAlexander Richardson2018-06-2510-26/+13
* AMDGPU/GlobalISel: Add support for llvm.amdgcn.kernarg.segment.ptrMatt Arsenault2018-06-253-1/+29
* StackSlotColoring: Decide colors per stack IDMatt Arsenault2018-06-251-22/+50
* AMDGPU: Remove commented out codeMatt Arsenault2018-06-251-2/+0
* AMDGPU/GlobalISel: Fix G_IMPLICIT_DEF for pointersMatt Arsenault2018-06-251-1/+5
* [SampleFDO] Add an option to turn on/off warning about samples unused.Wei Mi2018-06-251-0/+8
* [DA] Delinearise AddRecs if we can prove they don't wrapDavid Green2018-06-251-2/+21
* AMDGPU: Respect align argument parameterMatt Arsenault2018-06-252-10/+19
* SafepointIRVerifier should ignore dead blocks and dead edgesArtur Pilipenko2018-06-251-28/+189
* Improve handling of COPY instructions with identical value numbersKrzysztof Parzyszek2018-06-251-28/+126
* Revert change 335077 "[InlineSpiller] Fix a crash due to lack of forward prog...Artur Pilipenko2018-06-251-26/+0
* Use APInt[] bit access to avoid "32-bit shift implicitly converted to 64 bits...Simon Pilgrim2018-06-251-1/+1
* Use APInt[] bit access to avoid "32-bit shift implicitly converted to 64 bits...Simon Pilgrim2018-06-251-1/+1
* Fix -Wparentheses gcc warning. NFCI.Simon Pilgrim2018-06-251-1/+1
* [X86] Block commuting operand 1 of FMA*_Int instructions in findThreeSrcCommu...Craig Topper2018-06-252-88/+47
* [MSSA] Add domination number verifier; NFCGeorge Burgess IV2018-06-251-0/+39
* [WebAssembly] Add WebAssemblyException information analysisHeejin Ahn2018-06-255-0/+370
* [WebAssembly] Add WebAssemblyLateEHPrepare passHeejin Ahn2018-06-255-93/+388
* [X86] Simplify some code by using isOneConstant. NFCCraig Topper2018-06-251-2/+1
* [X86] Remove the changes to combineScalarToVector made in r335037.Craig Topper2018-06-251-26/+3
* [X86] Reduce the number of patterns needed for masked scalar ceil/floor isel.Craig Topper2018-06-251-35/+10
* [mips][ias] Enable IAS by default for OpenBSD / FreeBSD mips64/mips64el.Brad Smith2018-06-241-0/+5
* [DAGCombiner] eliminate setcc bool math when input is low-bit of some valueSanjay Patel2018-06-241-0/+45
* [X86] Regroup some isel patterns. NFCCraig Topper2018-06-241-32/+22
* [X86] Rename VFPCLASSSS and VFPCLASSSD internal instruction names to include ...Craig Topper2018-06-243-14/+14
* Add OpenBSD support to the Threading codeBrad Smith2018-06-231-3/+5
* ADT: Use EBO to shrink SmallVector size 1Duncan P. N. Exon Smith2018-06-231-0/+4
* [TableGen] Use WithColor for printing errors/warningsJonas Devlieghere2018-06-231-6/+3
* [X86] Make %eiz usage in 64-bit mode, force a 0x67 address size prefix. Fix s...Craig Topper2018-06-231-0/+2
* [X86] Teach disassembler to use %eip instead of %rip when 0x67 prefix is used...Craig Topper2018-06-231-1/+3
* [X86][AsmParser] Improve base/index register checks.Craig Topper2018-06-231-8/+29
* Fix invariant fdiv hoisting in LICMStanislav Mekhanoshin2018-06-231-14/+14
* [AMDGPU] Update includes for intrinsic changes :(Reid Kleckner2018-06-232-4/+4
* [ORC] Fix formatting and list pending queries in VSO::dump.Lang Hames2018-06-231-3/+7
* [IR] Split Intrinsics.inc into enums and implementationsReid Kleckner2018-06-232-8/+9
* [X86][AsmParser] Rework that allows (%dx) to be used in place of %dx with in/...Craig Topper2018-06-231-41/+29
* [RuntimeDyld] Implement the ELF PIC large code model relocationsReid Kleckner2018-06-221-0/+43
* [LoopReroll] Rewrite induction variable rewriting.Eli Friedman2018-06-221-177/+59
* [MSSA] Remove incorrect comment + `auto`ify dyn_cast results; NFCGeorge Burgess IV2018-06-221-6/+5
* [X86][AsmParser] Keep track of whether an explicit scale was specified while ...Craig Topper2018-06-221-8/+16
* [X86][AsmParser] In Intel syntax make sure we support ESP/RSP being the secon...Craig Topper2018-06-221-0/+4
* Re-land "[LTO] Enable module summary emission by default for regular LTO"Tobias Edler von Koch2018-06-221-1/+5
* [X86] Don't accept (%si,%bp) 16-bit address expressions.Craig Topper2018-06-221-4/+9
* [X86][AsmParser] Allow (%bp,%si) and (%bp,%di) to be encoded without using a ...Craig Topper2018-06-221-1/+1
* [X86][AsmParser] Check for invalid 16-bit base register in Intel syntax.Craig Topper2018-06-221-19/+24
* [X86] Don't allow ESP/RSP to be used as an index register in assembly.Craig Topper2018-06-221-1/+2
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