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* Print out register class of spilled register.Jakob Stoklund Olesen2010-10-301-2/+4
| | | | llvm-svn: 117761
* Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson2010-10-305-131/+61
| | | | | | | | | | | | | | | | | | | There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. llvm-svn: 117756
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-304-0/+23
| | | | llvm-svn: 117753
* Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling2010-10-291-3/+9
| | | | | | conditional. Check for those instructions explicitly. llvm-svn: 117747
* Teach machine cse to eliminate instructions with multiple physreg uses and ↵Evan Cheng2010-10-291-50/+45
| | | | | | defs. rdar://8610857. llvm-svn: 117745
* Remove hard tab characters.Jim Grosbach2010-10-291-3/+3
| | | | llvm-svn: 117742
* 80 column fix.Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117741
* trailing whitespaceJim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117740
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-293-3/+3
| | | | | | encoder functions. llvm-svn: 117738
* Fix fpscr <-> GPR latency info.Evan Cheng2010-10-293-4/+12
| | | | llvm-svn: 117737
* Be more strict on when we produce an undefined reference. In gas a file withRafael Espindola2010-10-291-1/+4
| | | | | | | | | | | | | | | | | | | | | | | just .type foo,@object will produce an undefined reference to foo. On the other hand, a file with just .weakref bar, foo will not. It is somewhat hard to support both in MC since both statements should create the symbols. It should be possible if we really need to by adding to the flags, but hopefully that is not necessary. With this patch we do not produce a undefined reference in any of those cases. The assembly file needs an actual use for the undefined reference to be present. This is in preparation for a patch implementing .weakref. llvm-svn: 117735
* Clean up indentation and other whitespace.Bob Wilson2010-10-291-11/+9
| | | | llvm-svn: 117728
* Remove trailing whitespace.Bob Wilson2010-10-291-70/+69
| | | | llvm-svn: 117727
* Fix 80-column violation.Bob Wilson2010-10-291-1/+2
| | | | llvm-svn: 117722
* Change instcombine's getShuffleMask to represent undef with negative values.Bob Wilson2010-10-291-40/+36
| | | | | | | | This code had previously used 2*N, where N is the mask length, to represent undef. That is not safe because the shufflevector operands may have more than N elements -- they don't have to match the result type. llvm-svn: 117721
* Remove DAG combiner patch to fold vector splats. Instcombiner does it now.Bob Wilson2010-10-291-5/+0
| | | | llvm-svn: 117720
* Make instcombine a little more aggressive in combining vector shuffles.Bob Wilson2010-10-291-15/+22
| | | | | | | | Allow splats even if they don't match either of the original shuffles, possibly due to undef entries in the shuffles masks. Radar 8597790. Also fix some 80-column violations. llvm-svn: 117719
* add FIXMEJim Grosbach2010-10-291-0/+5
| | | | llvm-svn: 117718
* Convert ARM::MOVi2pieces to a true pseudo-instruction and expand it inJim Grosbach2010-10-294-45/+32
| | | | | | the ARMExpandPseudos pass rather than during the asm lowering. llvm-svn: 117714
* Handle comparison values we already have - this fixes the consumer-typesetEric Christopher2010-10-291-4/+65
| | | | | | failure for llvm-gcc on arm fast isel. llvm-svn: 117710
* Give up on doing in-line instruction simplification during correlated value ↵Owen Anderson2010-10-291-10/+1
| | | | | | | | | | | | | propagation. Instruction simplification needs to be guaranteed never to be run on an unreachable block. However, earlier block simplifications may have changed the CFG to make block that were reachable when we began our iteration unreachable by the time we try to simplify them. (Note that this also means that our depth-first iterators were potentially being invalidated). This should not have a large impact on code quality, since later runs of instcombine should pick up these simplifications. Fixes PR8506. llvm-svn: 117709
* ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need toJim Grosbach2010-10-291-55/+0
| | | | | | handle it in the asm lowering. llvm-svn: 117707
* Fix typo.Jim Grosbach2010-10-291-1/+1
| | | | llvm-svn: 117703
* ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj ↵Jim Grosbach2010-10-292-20/+25
| | | | | | pseudos and a FIXME for TLS. llvm-svn: 117702
* Make ScalarEvolution::forgetLoop forget all contained loops too, becauseDan Gohman2010-10-291-0/+5
| | | | | | | they may have ValuesAtScopes map entries referencing their outer loops. This fixes a user-after-free reported in PR8471. llvm-svn: 117698
* ARM mode LDREX*/STREX* binary encodings.Jim Grosbach2010-10-292-18/+28
| | | | llvm-svn: 117695
* Encoding information for ARM conditional move instructions.Jim Grosbach2010-10-291-19/+35
| | | | llvm-svn: 117687
* Fix sign error.Jakob Stoklund Olesen2010-10-291-1/+1
| | | | llvm-svn: 117677
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-293-26/+85
| | | | | | | | | | | | | | | | | | | | | | | | | operand and one of them has a single use that is a live out copy, favor the one that is live out. Otherwise it will be difficult to eliminate the copy if the instruction is a loop induction variable update. e.g. BB: sub r1, r3, #1 str r0, [r2, r3] mov r3, r1 cmp bne BB => BB: str r0, [r2, r3] sub r3, r3, #1 cmp bne BB This fixed the recent 256.bzip2 regression. llvm-svn: 117675
* - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.Evan Cheng2010-10-291-3/+7
| | | | | | - Compute CopyToReg use operand latency correctly. llvm-svn: 117674
* Don't transfer unused values to the new intervals formed by splitting.Jakob Stoklund Olesen2010-10-291-0/+3
| | | | llvm-svn: 117673
* Handle ARM addrmode5 instructions with an offset.Jim Grosbach2010-10-291-9/+24
| | | | llvm-svn: 117672
* Silence Release build warnings.Benjamin Kramer2010-10-291-4/+3
| | | | llvm-svn: 117671
* Teach ConnectedVNInfoEqClasses::Classify to deal with unused values.Jakob Stoklund Olesen2010-10-291-1/+15
| | | | | | | | We don't want unused values forming their own equivalence classes, so we lump them all together in one class, and then merge them with the class of the last used value. llvm-svn: 117670
* Never propagate the idom value out of a block that defines its own value.Jakob Stoklund Olesen2010-10-291-3/+7
| | | | llvm-svn: 117669
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-2923-78/+477
| | | | | | basic logic, added initial platform support. llvm-svn: 117667
* Check if ErrMsg is null. This fixes the "not" command.Dan Gohman2010-10-291-6/+11
| | | | llvm-svn: 117666
* Fix these error messages to be less confusing. These errorDan Gohman2010-10-291-9/+5
| | | | | | | messages primarily indicate errors running the viewer, not errors with the graph file itself. llvm-svn: 117665
* Make Program::Wait differentiate execution failure due to the fileDan Gohman2010-10-293-9/+13
| | | | | | being not found from the file being not executable. llvm-svn: 117664
* Revert 117660. Apparently it's not as trivial as that...Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117663
* Make Program::Wait provide an error message string for errorsDan Gohman2010-10-291-9/+19
| | | | | | executing the child process and abnormal child process termination. llvm-svn: 117661
* ARM addrmode5 instructions have neither writeback nor post-indexed modes.Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117660
* Trailing whitespace.Jim Grosbach2010-10-291-30/+30
| | | | llvm-svn: 117651
* ARMAsmParser: Plug a memory leak.Benjamin Kramer2010-10-291-2/+3
| | | | llvm-svn: 117648
* Add an unreachable to silence warning - the switch is actuallyEric Christopher2010-10-291-0/+2
| | | | | | fully enumerated. llvm-svn: 117647
* This may be an ARM target, so check for _Unwind_SjLj_Resume.Bill Wendling2010-10-291-11/+15
| | | | llvm-svn: 117643
* Teach memdep to use pointsToConstantMemory to determine that loadsDan Gohman2010-10-291-5/+10
| | | | | | from constant memory don't alias any stores. llvm-svn: 117636
* Fix broken equivalence class calculation. We could probably also useJakob Stoklund Olesen2010-10-291-11/+8
| | | | | | | EquvivalenceClasses.h except it looks like overkill when elements are continuous integers. llvm-svn: 117631
* Print out the connected components in the verifier after complaining about theirJakob Stoklund Olesen2010-10-291-0/+8
| | | | | | multiplicity. llvm-svn: 117630
* Run a verification pass before any splitting to better distribute blame.Jakob Stoklund Olesen2010-10-291-0/+2
| | | | llvm-svn: 117629
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