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authorJim Grosbach <grosbach@apple.com>2010-10-29 16:38:59 +0000
committerJim Grosbach <grosbach@apple.com>2010-10-29 16:38:59 +0000
commit8682b69b81b802232f4b1c81270ff0ecb4b4353a (patch)
tree778e0e9696cef6db08e2b98f11348754fdf4eb92 /llvm/lib
parent31d1e2153f6625f504d5d551f17c3e076ff269eb (diff)
downloadbcm5719-llvm-8682b69b81b802232f4b1c81270ff0ecb4b4353a.tar.gz
bcm5719-llvm-8682b69b81b802232f4b1c81270ff0ecb4b4353a.zip
ARM addrmode5 instructions have neither writeback nor post-indexed modes.
llvm-svn: 117660
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index b09dcd080f1..857352bfea1 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -236,9 +236,9 @@ public:
bool isMemMode5() const {
- // FIXME: Is this right? What about postindexed and Writeback?
if (!isMemory() || Mem.OffsetIsReg || Mem.OffsetRegShifted ||
- Mem.Preindexed || Mem.Negative)
+ Mem.Preindexed || Mem.Negative || Mem.Postindexed ||
+ Mem.Writeback)
return false;
return true;
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