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* [GVN] Prevent ScalarPRE from hoisting across instructions that don't pass ↵Max Kazantsev2017-11-281-0/+14
| | | | | | | | | | | | control flow to successors This is to address a problem similar to those in D37460 for Scalar PRE. We should not PRE across an instruction that may not pass execution to its successor unless it is safe to speculatively execute it. Differential Revision: https://reviews.llvm.org/D38619 llvm-svn: 319147
* [WebAssembly] Handle errors better in fast-isel.Dan Gohman2017-11-281-12/+40
| | | | | | | | | Fast-isel routines need to bail out in the case that fast-isel fails on the operands. This fixes https://bugs.llvm.org/show_bug.cgi?id=35064 llvm-svn: 319144
* [X86] Remove some unused pattern fragments from td file. NFCCraig Topper2017-11-281-10/+0
| | | | llvm-svn: 319143
* [DAGCombine] Disable finding better chains for stores at O0Simon Dardis2017-11-281-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Unoptimized IR can have linear sequences of stores to an array, where the initial GEP for the first store is formed from the pointer to the array, and the GEP for each store after the first is formed from the previous GEP with some offset in an inductive fashion. The (large) resulting DAG when analyzed by DAGCombine undergoes an excessive number of combines as each store node is examined every time its' offset node is combined with any child of the offset. One of the transformations is findBetterNeighborChains which assists MergeConsecutiveStores. The former relies on repeated chain walking to do its' work, however MergeConsecutiveStores is disabled at O0 which makes the transformation redundant. Any optimization level other than O0 would invoke InstCombine which would resolve the chain of GEPs into flat base + offset GEP for each store which does not exhibit the repeated examination of each store to the array. Disabling this optimization fixes an excessive compile time issue (30~ minutes for the test case provided) at O0. Reviewers: niravd, craig.topper, t.p.northover Differential Revision: https://reviews.llvm.org/D40193 llvm-svn: 319142
* MachineVerifier: Improve register operand checksMatthias Braun2017-11-281-78/+81
| | | | | | | | | | | | This fixes cases where we wouldn't perform various register operand checks just because we didn't happen to have a definition in the MCInstrDesc. This changes the code to only skip the tests that actually depend on the MCInstrDesc definition. This makes the machine verifier spot the problem from https://llvm.org/PR33071 after the pass that actually caused it. llvm-svn: 319141
* MachineVerifier: Improve PHI operand checkingMatthias Braun2017-11-281-28/+54
| | | | | | | | | | | | Additional checks for phi operands: - first operand should be a virtual register def. It should not be tied, implicit, internalread, earlyclobber or a read. - The other operands should be register/mbb operands next to each other - The register operands should not be implicit, internalread, earlyclobber, debug or tied. - We can perform most of the PHI checks even for unreachable blocks. llvm-svn: 319140
* Use FILE_FLAG_DELETE_ON_CLOSE for TempFile on windows.Rafael Espindola2017-11-282-6/+80
| | | | | | We won't see the temp file no more. llvm-svn: 319137
* [X86] Make zero extend from v16i1/v8i1 to v16i8/v8i16/v16i16 not scalarize ↵Craig Topper2017-11-281-0/+4
| | | | | | under AVX512. llvm-svn: 319136
* Move code. NFC.Rafael Espindola2017-11-281-83/+85
| | | | | | | This moves the TempFile implementation so that it can use system specific code. llvm-svn: 319134
* This reverts commit r319096 and r319097.Rafael Espindola2017-11-283-165/+34
| | | | | | | | | Revert "[SROA] Propagate !range metadata when moving loads." Revert "[Mem2Reg] Clang-format unformatted parts of this file. NFCI." Davide says they broke a bot. llvm-svn: 319131
* ARM: Fix PR32578Matthias Braun2017-11-281-1/+1
| | | | | | | | | | https://llvm.org/PR32578 I simplified and converted the reproducer into a lit test. Patch by Vedant Kumar! llvm-svn: 319130
* [WebAssembly] Fix trapping behavior in fptosi/fptoui.Dan Gohman2017-11-288-19/+227
| | | | | | | | | | | | This adds code to protect WebAssembly's `trunc_s` family of opcodes from values outside their domain. Even though such conversions have full undefined behavior in C/C++, LLVM IR's `fptosi` and `fptoui` do not, and only return undef. This also implements the proposed non-trapping float-to-int conversion feature and uses that instead when available. llvm-svn: 319128
* SROA: Avoid creating a fragment expression that covers the entire variable.Adrian Prantl2017-11-281-4/+9
| | | | | | | | Fixes PR35416. https://bugs.llvm.org/show_bug.cgi?id=35416 llvm-svn: 319126
* Move getVariableSize from Verifier.cpp into DIVariable::getSize() (NFC)Adrian Prantl2017-11-282-26/+26
| | | | llvm-svn: 319125
* [X86] Remove unnecessary fp<->int setOperationAction lines from a hasVLX ↵Craig Topper2017-11-281-7/+0
| | | | | | | | block. NFCI These lines all exist identically either under SSE2, AVX2 or AVX512. Given that VLX implies all of those, these aren't providing anything new. llvm-svn: 319124
* [X86] Remove duplicate calls to setOperationAction. NFCICraig Topper2017-11-281-2/+0
| | | | | | These same calls exist a few lines down. llvm-svn: 319122
* Add an F_Delete flag.Rafael Espindola2017-11-281-0/+2
| | | | | | For now this only changes the handle Access. llvm-svn: 319121
* [DAGCombiner] Don't combine aext(setcc) if the setcc is already using the ↵Craig Topper2017-11-271-8/+11
| | | | | | | | | | target's preferred result type. With AVX512 vXi1 types are legal so we shouldn't be extending them. This change is similar to existing code in the zext(setcc) combine. llvm-svn: 319120
* [DAGCombiner] Use EVT::changeVectorElementTypeToInteger() instead of ↵Craig Topper2017-11-271-4/+1
| | | | | | implementing manually. llvm-svn: 319119
* Add OpenFlags to the create(Unique|Temporary)File interfaces.Rafael Espindola2017-11-271-14/+20
| | | | | | | This will allow a future F_Delete flag to be specified when we want the file to be automatically deleted on close. llvm-svn: 319117
* [X86] Teach getSetCCResultType to handle more than just SimpleVTs when ↵Craig Topper2017-11-271-15/+12
| | | | | | | | looking at larger than 512-bit vectors. Which VTs are considered simple is determined by the superset of the legal types of all targets in LLVM. If we're looking at VTs that are going to be split down to 512-bits we should allow any VT not just simple ones since the simple list changes over time as new targets are added. llvm-svn: 319110
* Fixed the ability to recursively get an attribute value from a DWARFDie.Greg Clayton2017-11-271-10/+9
| | | | | | | | The previous implementation would only look 1 DW_AT_specification or DW_AT_abstract_origin deep. This means DWARFDie::getName() would fail in certain cases. I ran into such a case while creating a tool that used the LLVM DWARF parser to generate a symbolication format so I have seen this in the wild. Differential Revision: https://reviews.llvm.org/D40156 llvm-svn: 319104
* [X86] Remove lines that set v8f32 FP_ROUND/FP_EXTEND to Legal under AVX512. NFCICraig Topper2017-11-271-2/+0
| | | | | | We don't do this for narrow vectors under AVX or SSE features. We also don't set them to Expand like we do for many vectors op. Nor does TargetLoweringBase.cpp. This leads me to believe these default to Legal. llvm-svn: 319103
* [Mem2Reg] Clang-format unformatted parts of this file. NFCI.Davide Italiano2017-11-271-28/+23
| | | | llvm-svn: 319097
* [SROA] Propagate !range metadata when moving loads.Davide Italiano2017-11-273-32/+168
| | | | | | | | | | | | | This tries to propagate !range metadata to a pre-existing load when a load is optimized out. This is done instead of adding an assume because converting loads to and from assumes creates a lot of IR. Patch by Ariel Ben-Yehuda. Differential Revision: https://reviews.llvm.org/D37216 llvm-svn: 319096
* [PartiallyInlineLibCalls][x86] add TTI hook to allow sqrt inlining to depend ↵Sanjay Patel2017-11-274-5/+19
| | | | | | | | | | | on arg rather than result This should fix PR31455: https://bugs.llvm.org/show_bug.cgi?id=31455 Differential Revision: https://reviews.llvm.org/D28314 llvm-svn: 319094
* [PowerPC] Remove redundant TOC savesZaara Syeda2017-11-273-2/+87
| | | | | | | | | | This patch adds a peep hole optimization to remove any redundant toc save instructions added as part of the call sequence for indirect calls. It removes any toc saves within a function that are dominated by another toc save. Differential Revision: https://reviews.llvm.org/D39736 llvm-svn: 319087
* [SelectionDAG] Add a debug message when vector_shuffle nodes are created.Craig Topper2017-11-271-1/+3
| | | | | | We print a debug message when most nodes are created, but getVectorShuffle was missing. llvm-svn: 319085
* Inliner: Don't mark notail calls with the 'tail' attributeArnold Schwaighofer2017-11-271-1/+2
| | | | | | | | | | | | enum TailCallKind { TCK_None = 0, TCK_Tail = 1, TCK_MustTail = 2, TCK_NoTail = 3 }; TCK_NoTail is greater than TCK_Tail so taking the min does not do the correct thing. rdar://35639547 llvm-svn: 319075
* [BinaryStream] Support growable streams.Zachary Turner2017-11-273-13/+14
| | | | | | | | | The existing library assumed that a stream's length would never change. This makes some things simpler, but it's not flexible enough for what we need, especially for writable streams where what you really want is for each call to write to actually append. llvm-svn: 319070
* [X86] Remove an unused isel pattern that looked for pshufd with v4f32 type.Craig Topper2017-11-271-12/+0
| | | | | | I don't believe our current lowering/combining would ever produce such a node. We only produce integer typed pshufds. llvm-svn: 319068
* [InstCombine] use 'auto' with 'dyn_cast'; NFCSanjay Patel2017-11-271-3/+2
| | | | llvm-svn: 319067
* [X86] Teach combineX86ShuffleChain that AllowIntDomain requires at least SSE2.Craig Topper2017-11-271-1/+1
| | | | | | I don't have a good test case for this at the moment. I was playing around with a change in legalizing and triggered this code to produce a PSHUFD with sse1 only. llvm-svn: 319066
* [X86][AVX512] Tag AVX512 PACKSS/PACKUS/PMADDWD/PMADDUBSW instructions with ↵Simon Pilgrim2017-11-272-20/+29
| | | | | | | | SSE_PACK/SSE_PMADD schedule classes llvm-svn: 319065
* [Hexagon] Implement HexagonSubtarget::isHVXVectorTypeKrzysztof Parzyszek2017-11-272-27/+14
| | | | llvm-svn: 319064
* [X86] Make getSetCCResultType return vXi1 for any vXi32/vXi64 vector over ↵Craig Topper2017-11-271-1/+1
| | | | | | | | | | 512 bits long when AVX512 is enabled. Similar for vXi16/vXi8 with BWI. Any vector larger than 512 bits will be split to 512 bits during legalization. But without this we will fold sexts with them before that making it difficult to recover leading to scalarization. llvm-svn: 319059
* [X86][SSE] Fix roundpd instructions to correctly use IIC_SSE_ROUNDPD_* ↵Simon Pilgrim2017-11-271-2/+2
| | | | | | itineraries llvm-svn: 319054
* [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodesDmitry Preobrazhensky2017-11-273-6/+6
| | | | | | | | | See bug 35433: https://bugs.llvm.org/show_bug.cgi?id=35433 Differential Revision: https://reviews.llvm.org/D40493 Reviewers: artem.tamazov, SamWot, arsenm llvm-svn: 319050
* [Power9] Improvements to vector extract with variable index exploitationZaara Syeda2017-11-271-22/+174
| | | | | | | | | | This patch extends on to rL307174 to not use the power9 vector extract with variable index instructions when extracting word element 1. For such cases, the existing selection of MFVSRWZ provides a better sequence. Differential Revision: https://reviews.llvm.org/D38287 llvm-svn: 319049
* [X86][AVX512] Tag AVX512 sqrt instructions with SSE_SQRT schedule classesSimon Pilgrim2017-11-271-29/+32
| | | | llvm-svn: 319045
* [llvm-dwarfdump] Display DW_AT_high_pc as absolute valueJonas Devlieghere2017-11-271-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | DWARF4 relative DW_AT_high_pc values are now displayed as absolute addresses. The relative value is only shown when explicitly dumping the forms, i.e. in show-form or verbose mode. ``` DW_AT_low_pc (0x0000000000000049) DW_AT_high_pc (0x00000019) ``` becomes ``` DW_AT_low_pc (0x0000000000000049) DW_AT_high_pc (0x0000000000000062) ``` Differential revision: https://reviews.llvm.org/D40317 rdar://35416943 llvm-svn: 319044
* [InstSimplify] use m_APFloat to simplify fcmp folds; NFCISanjay Patel2017-11-271-13/+7
| | | | llvm-svn: 319043
* [DAG] Do MergeConsecutiveStores again before Instruction SelectionNirav Dave2017-11-271-2/+0
| | | | | | | | | | | | | | | | Summary: Now that store-merge is only generates type-safe stores, do a second pass just before instruction selection to allow lowered intrinsics to be merged as well. Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33675 llvm-svn: 319036
* [X86] Add INVLPGA to the existing INVLPG schedulingSimon Pilgrim2017-11-271-3/+4
| | | | llvm-svn: 319031
* [mips] fix asmstring of Ext and Ins instructions and mips16 JALRC/JRCPetar Jovanovic2017-11-272-5/+5
| | | | | | | | | | | | | | | Make the print format consistent with other assembler instructions. Adding a tab character instead of space in asmstring of Ext and Ins instructions. Removing space around the tab character for JALRC and replacing space with tab in JRC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D38144 llvm-svn: 319030
* [Support] Fix locking of shared variable in threadpoolJan Korous2017-11-271-1/+1
| | | | llvm-svn: 319027
* [AMDGPU] Add custom lowering for llvm.log{,10}.{f16,f32} intrinsicsVedran Miletic2017-11-272-0/+32
| | | | | | | | | | | | | | AMDGPU backend errors with "unsupported call to function" upon encountering a call to llvm.log{,10}.{f16,f32} intrinsics. This patch adds custom lowering to avoid that error on both R600 and SI. Reviewers: arsenm, jvesely Subscribers: tstellar Differential Revision: https://reviews.llvm.org/D29942 llvm-svn: 319025
* [CGP] Fix handling of null pointer values in optimizeMemoryInstJohn Brawn2017-11-271-9/+7
| | | | | | | | | | | The current way that trivial addressing modes are detected incorrectly thinks that null pointers are non-trivial, leading to an infinite loop where we keep duplicating the same select. Fix this by aware of null when deciding if an addressing mode is trivial. Differential Revision: https://reviews.llvm.org/D40447 llvm-svn: 319019
* [X86][FMA] Tag all FMA/FMA4 instructions with WriteFMA schedule classSimon Pilgrim2017-11-2710-52/+75
| | | | | | | | | | As mentioned on PR17367, many instructions are missing scheduling tags preventing us from setting 'CompleteModel = 1' for better instruction analysis. This patch deals with FMA/FMA4 which is one of the bigger offenders (along with AVX512 in general). Annoyingly all scheduler models need to define WriteFMA (now that its actually used), even for older targets without FMA/FMA4 support, but that is an existing problem shared by other schedule classes. Differential Revision: https://reviews.llvm.org/D40351 llvm-svn: 319016
* [ARM] Fix an off-by-one error when restoring LR for 16-bit ThumbMomchil Velikov2017-11-271-1/+1
| | | | | | | | | | | | | | The commit https://reviews.llvm.org/rL318143 computes incorrectly to offset to restore LR from. The number of tPOP operands is 2 (condition) + 2 (implicit def and use of SP) + count of the popped registers. We need to load LR from just past the last register, hence the correct offset should be either getNumOperands() - 4 and getNumExplicitOperands() - 2 (multiplied by 4). Differential revision: https://reviews.llvm.org/D40305 llvm-svn: 319014
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