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| author | Nirav Dave <niravd@google.com> | 2017-11-27 15:28:15 +0000 |
|---|---|---|
| committer | Nirav Dave <niravd@google.com> | 2017-11-27 15:28:15 +0000 |
| commit | db77e57ea86d941a4262ef60261692f4cb6893e6 (patch) | |
| tree | 5ea93e1652b4f3065657d9618c69315582b377a4 /llvm/lib | |
| parent | 948a915924ded9364ddf2d55ad69f47b37bc0843 (diff) | |
| download | bcm5719-llvm-db77e57ea86d941a4262ef60261692f4cb6893e6.tar.gz bcm5719-llvm-db77e57ea86d941a4262ef60261692f4cb6893e6.zip | |
[DAG] Do MergeConsecutiveStores again before Instruction Selection
Summary:
Now that store-merge is only generates type-safe stores, do a second
pass just before instruction selection to allow lowered intrinsics to
be merged as well.
Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33675
llvm-svn: 319036
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 4481e073bb1..589abaa5f7c 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -9562,8 +9562,6 @@ static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode &St) { static SDValue splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) { - if (!DCI.isBeforeLegalize()) - return SDValue(); StoreSDNode *S = cast<StoreSDNode>(N); if (S->isVolatile() || S->isIndexed()) |
