summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* DataFlowSanitizer: Prefix the name of each instrumented function with "dfs$".Peter Collingbourne2013-08-221-7/+51
| | | | | | | | | | | | | | | | DFSan changes the ABI of each function in the module. This makes it possible for a function with the native ABI to be called with the instrumented ABI, or vice versa, thus possibly invoking undefined behavior. A simple way of statically detecting instances of this problem is to prepend the prefix "dfs$" to the name of each instrumented-ABI function. This will not catch every such problem; in particular function pointers passed across the instrumented-native barrier cannot be used on the other side. These problems could potentially be caught dynamically. Differential Revision: http://llvm-reviews.chandlerc.com/D1373 llvm-svn: 189052
* [ARMv8] Add CodeGen support for VSEL.Joey Gouly2013-08-222-9/+105
| | | | | | | | This uses the ARMcmov pattern that Tim cleaned up in r188995. Thanks to Simon Tatham for his floating point help! llvm-svn: 189024
* [Win32] mapped_file_region: Fix a bug in CreateFileMapping() that Size must ↵NAKAMURA Takumi2013-08-221-2/+2
| | | | | | contain Offset when Offset >= 65536. llvm-svn: 189021
* Whitespace.NAKAMURA Takumi2013-08-221-3/+3
| | | | llvm-svn: 189020
* Fix ARM vcvt encoding when the number of fractional bits is zero.Mihai Popa2013-08-221-0/+19
| | | | | | | | | | | The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. llvm-svn: 189009
* Teach the SLP vectorizer the correct way to check for consecutive accessChandler Carruth2013-08-221-49/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | using GEPs. Previously, it used a number of different heuristics for analyzing the GEPs. Several of these were conservatively correct, but failed to fall back to SCEV even when SCEV might have given a reasonable answer. One was simply incorrect in how it was formulated. There was good code already to recursively evaluate the constant offsets in GEPs, look through pointer casts, etc. I gathered this into a form code like the SLP code can use in a previous commit, which allows all of this code to become quite simple. There is some performance (compile time) concern here at first glance as we're directly attempting to walk both pointers constant GEP chains. However, a couple of thoughts: 1) The very common cases where there is a dynamic pointer, and a second pointer at a constant offset (usually a stride) from it, this code will actually not do any unnecessary work. 2) InstCombine and other passes work very hard to collapse constant GEPs, so it will be rare that we iterate here for a long time. That said, if there remain performance problems here, there are some obvious things that can improve the situation immensely. Doing a vectorizer-pass-wide memoizer for each individual layer of pointer values, their base values, and the constant offset is likely to be able to completely remove redundant work and strictly limit the scaling of the work to scrape these GEPs. Since this optimization was not done on the prior version (which would still benefit from it), I've not done it here. But if folks have benchmarks that slow down it should be straight forward for them to add. I've added a test case, but I'm not really confident of the amount of testing done for different access patterns, strides, and pointer manipulation. llvm-svn: 189007
* [ARM] Constrain some register classes in EmitAtomicBinary64 so thatJoey Gouly2013-08-221-0/+4
| | | | | | we pass these tests with -verify-machineinstrs. llvm-svn: 189006
* AVX-512: Added masked SHIFT commands, more encoding testsElena Demikhovsky2013-08-222-23/+44
| | | | llvm-svn: 189005
* Fix ARM FastISel PIC function call.Logan Chien2013-08-221-2/+9
| | | | | | | The function call to external function should come with PLT relocation type if the PIC relocation model is used. llvm-svn: 189002
* Add a new helper method to Value to strip in-bounds constant offsets ofChandler Carruth2013-08-221-0/+34
| | | | | | | | | | | pointers, but accumulate the offset into an APInt in the process of stripping it. This is a pretty handy thing to have, such as when trying to determine if two pointers are at some constant relative offset. I'll be committing a patch shortly to use it for exactly that purpose. llvm-svn: 189000
* MemoryBuffer.cpp: Consider if PageSize were not 4096 in shouldUseMmap(). ↵NAKAMURA Takumi2013-08-221-1/+1
| | | | | | | | Follow-up to r188903. The AllocationGranularity can be 65536 on Win32, even on Cygwin. llvm-svn: 188998
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-227-326/+137
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
* ARM: respect tied 64-bit inlineasm operands when printingTim Northover2013-08-221-0/+17
| | | | | | | The code for 'Q' and 'R' operand modifiers needs to look through tied operands to discover the register class. llvm-svn: 188990
* [stackprotector] When finding the split point to splice off the end of a ↵Michael Gottesman2013-08-221-9/+44
| | | | | | | | parentmbb into a successmbb, include any DBG_VALUE MI. Fix for PR16954. llvm-svn: 188987
* Teach LoopVectorize about address space sizesMatt Arsenault2013-08-221-1/+2
| | | | llvm-svn: 188980
* ARM: R9 is not safe to use for tcGPR.Jim Grosbach2013-08-221-1/+1
| | | | | | | | | Indirect tail-calls shouldn't use R9 for the branch destination, as it's not reliably a call-clobbered register. rdar://14793425 llvm-svn: 188967
* Fixed typo.Michael Gottesman2013-08-211-1/+1
| | | | llvm-svn: 188957
* Removed trailing whitespace.Michael Gottesman2013-08-211-13/+13
| | | | llvm-svn: 188956
* SelectionDAG: Make sure stores are always added to the LegalizedNodes listTom Stellard2013-08-211-1/+1
| | | | | | | | | | | | | | | | When truncated vector stores were being custom lowered in VectorLegalizer::LegalizeOp(), the old (illegal) and new (legal) node pair was not being added to LegalizedNodes list. Instead of the legalized result being passed to VectorLegalizer::TranslateLegalizeResult(), the result was being passed back into VectorLegalizer::LegalizeOp(), which ended up adding a (new, new) pair to the list instead. This was causing an assertion failure when a custom lowered truncated vector store was the last instruction a basic block and the VectorLegalizer was unable to find it in the LegalizedNodes list when updating the DAG root. llvm-svn: 188953
* R600: Remove unnecessary castsTom Stellard2013-08-211-8/+6
| | | | | | Spotted by Bill Wendling. llvm-svn: 188942
* No functionality change.Yunzhong Gao2013-08-211-2/+2
| | | | | | Replace "(255 & value)" with "(0xFF & value)" to improve clarity. llvm-svn: 188941
* Teach BaseIndexOffset::match to identify base pointers in loops.Juergen Ributzka2013-08-211-2/+14
| | | | | | | | | | | | | | The small utility function that pattern matches Base + Index + Offset patterns for loads and stores fails to recognize the base pointer for loads/stores from/into an array at offset 0 inside a loop. As a result DAGCombiner::MergeConsecutiveStores was not able to merge all stores. This commit fixes the issue by adding an additional pattern match and also a test case. Reviewer: Nadav llvm-svn: 188936
* Reorder headers according to lint.Bill Wendling2013-08-212-10/+6
| | | | llvm-svn: 188932
* Remove use of forbidden 'iostream' header.Bill Wendling2013-08-211-13/+11
| | | | | | Also obsessively reorder the headers to be in something closer to alphabetical order. llvm-svn: 188928
* Teach InstCombine about address spacesMatt Arsenault2013-08-212-21/+33
| | | | llvm-svn: 188926
* MC CFG: Remap enough for data too, analoguous to r188873.Ahmed Bougacha2013-08-211-1/+1
| | | | llvm-svn: 188925
* Style cleanup following David's review for r188876.Ahmed Bougacha2013-08-211-5/+4
| | | | llvm-svn: 188924
* Use attribute helper functionMatt Arsenault2013-08-211-2/+1
| | | | llvm-svn: 188916
* Fix typoMatt Arsenault2013-08-211-1/+1
| | | | llvm-svn: 188915
* A minor change for an obvous problem caused by r188451:Hao Liu2013-08-211-1/+1
| | | | | | | def imm0_63 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 63;}]>{ As it seems Imm <63 should be Imm <= 63. ImmLeaf is used in pattern match, but there is already a function check the shift amount range, so just remove ImmLeaf. Also add a test to check 63. llvm-svn: 188911
* Unix/Process.inc: Revert r72332, "Work around a page size issue on Cygwin."NAKAMURA Takumi2013-08-211-6/+3
| | | | | | | Offset in mmap(3) should be aligned to gepagesize(), 64k, or mmap(3) would fail. TODO: Invetigate places where 4096 would be required as pagesize, or 4096 would satisfy. llvm-svn: 188903
* Make "mov" work for all Thumb2 MOV encodingsMihai Popa2013-08-213-0/+17
| | | | | | | According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings. To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV. llvm-svn: 188901
* AVX-512: Added SHIFT instructions.Elena Demikhovsky2013-08-214-6/+178
| | | | llvm-svn: 188899
* [SystemZ] Define remainig *MUL_LOHI patternsRichard Sandiford2013-08-212-16/+73
| | | | | | | | | | | | | | | | | The initial port used MLG(R) for i64 UMUL_LOHI but left the other three combinations as not-legal-or-custom. Although 32x32->{32,32} multiplications exist, they're not as quick as doing a normal 64-bit multiplication, so it didn't seem like i32 SMUL_LOHI and UMUL_LOHI would be useful. There's also no direct instruction for i64 SMUL_LOHI, so it needs to be implemented in terms of UMUL_LOHI. However, not defining these patterns means that we don't convert division by a constant into multiplication, so this patch fills in the other cases. The new i64 SMUL_LOHI sequence is simpler than the one that we used previously for 64x64->128 multiplication, so int-mul-08.ll now tests the full sequence. llvm-svn: 188898
* [mips][msa] Matheus Almeida pointed out a silly mistake in r188893. Fixed it.Daniel Sanders2013-08-211-1/+1
| | | | | | | | | | I accidentally changed the encoding of the MSA registers to zero instead of 0 to 31. This change restores the encoding the registers had prior to r188893. This didn't show up in the existing tests because direct-object emission isn't implemented yet for MSA. llvm-svn: 188896
* [SystemZ] Use FI[EDX]BRA for codegenRichard Sandiford2013-08-212-0/+39
| | | | llvm-svn: 188895
* [SystemZ] Add FI[EDX]BRARichard Sandiford2013-08-215-10/+40
| | | | | | | These are extensions of the existing FI[EDX]BR instructions, but use a spare bit to suppress inexact conditions. llvm-svn: 188894
* [mips][msa] Define registers using foreachDaniel Sanders2013-08-211-32/+3
| | | | | | No functional change llvm-svn: 188893
* MC CFG: Add YAML MCModule representation to enable MC CFG testing.Ahmed Bougacha2013-08-212-0/+462
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like yaml ObjectFiles, this will be very useful for testing the MC CFG implementation (mostly MCObjectDisassembler), by matching the output with YAML, and for potential users of the MC CFG, by using it as an input. There isn't much to the actual format, it is just a serialization of the MCModule class. Of note: - Basic block references (pred/succ, ..) are represented by the BB's start address. - Just as in the MC CFG, instructions are MCInsts with a size. - Operands have a prefix representing the type (only register and immediate supported here). - Instruction opcodes are represented by their names; enum values aren't stable, enum names mostly are: usually, a change to a name would need lots of changes in the backend anyway. Same with registers. All in all, an example is better than 1000 words, here goes: A simple binary: Disassembly of section __TEXT,__text: _main: 100000f9c: 48 8b 46 08 movq 8(%rsi), %rax 100000fa0: 0f be 00 movsbl (%rax), %eax 100000fa3: 3b 04 25 48 00 00 00 cmpl 72, %eax 100000faa: 0f 8c 07 00 00 00 jl 7 <.Lend> 100000fb0: 2b 04 25 48 00 00 00 subl 72, %eax .Lend: 100000fb7: c3 ret And the (pretty verbose) generated YAML: --- Atoms: - StartAddress: 0x0000000100000F9C Size: 20 Type: Text Content: - Inst: MOV64rm Size: 4 Ops: [ RRAX, RRSI, I1, R, I8, R ] - Inst: MOVSX32rm8 Size: 3 Ops: [ REAX, RRAX, I1, R, I0, R ] - Inst: CMP32rm Size: 7 Ops: [ REAX, R, I1, R, I72, R ] - Inst: JL_4 Size: 6 Ops: [ I7 ] - StartAddress: 0x0000000100000FB0 Size: 7 Type: Text Content: - Inst: SUB32rm Size: 7 Ops: [ REAX, REAX, R, I1, R, I72, R ] - StartAddress: 0x0000000100000FB7 Size: 1 Type: Text Content: - Inst: RET Size: 1 Ops: [ ] Functions: - Name: __text BasicBlocks: - Address: 0x0000000100000F9C Preds: [ ] Succs: [ 0x0000000100000FB7, 0x0000000100000FB0 ] <snip> ... llvm-svn: 188890
* MC CFG: Support disassembly at arbitrary addresses in MCObjectDisassembler.Ahmed Bougacha2013-08-211-7/+206
| | | | llvm-svn: 188889
* MC CFG: Use data structures more appropriate than std::set.Ahmed Bougacha2013-08-211-10/+16
| | | | llvm-svn: 188888
* MC CFG: Add an MCObjectSymbolizer in the MCObjectDisassembler.Ahmed Bougacha2013-08-211-1/+2
| | | | | | Used to detect calls to function symbol stubs (future commit). llvm-svn: 188887
* MC CFG: Add MCObjectDisassembler Mach-O implementation.Ahmed Bougacha2013-08-211-0/+89
| | | | | | | | | | Supports: - entrypoint, using LC_MAIN. - static ctors/dtors, using __mod_{init,exit}_func - translation between effective and object load address, using dyld's VM address slide. llvm-svn: 188886
* MC CFG: Add "dynamic disassembly" support to MCObjectDisassembler.Ahmed Bougacha2013-08-211-1/+11
| | | | | | | | It can now disassemble code in situations where the effective load address is different than the load address declared in the object file. This happens for PIC, hence "dynamic". llvm-svn: 188884
* MC CFG: When disassembly is impossible, fallback to data bytes.Ahmed Bougacha2013-08-211-16/+30
| | | | | | | | | This is the behavior of sequential disassemblers (llvm-objdump, ...), when there is no instruction size hint (fixed-length, ...) While there, also do some minor cleanup. llvm-svn: 188883
* MC CFG: Add MCObjectDisassembler support for entrypoint + static ctors.Ahmed Bougacha2013-08-211-2/+49
| | | | | | For now, this isn't implemented for any format. llvm-svn: 188882
* MC CFG: Split MCBasicBlocks to mirror atom splitting.Ahmed Bougacha2013-08-213-2/+42
| | | | | | | | When an MCTextAtom is split, all MCBasicBlocks backed by it are automatically split, with a fallthrough between both blocks, and the successors moved to the second block. llvm-svn: 188881
* MC CFG: Add a few needed methods, mainly MCModule::findFirstAtomAfter.Ahmed Bougacha2013-08-212-5/+20
| | | | | | While there, do some minor cleanup. llvm-svn: 188880
* MC: ObjectSymbolizer can now recognize external function stubs.Ahmed Bougacha2013-08-211-1/+76
| | | | | | | Only implemented in the Mach-O ObjectSymbolizer. The testcase sadly introduces a new binary. llvm-svn: 188879
* MC: Refactor ObjectSymbolizer to make relocation/section info generation lazy.Ahmed Bougacha2013-08-211-100/+122
| | | | llvm-svn: 188878
OpenPOWER on IntegriCloud