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| author | Jim Grosbach <grosbach@apple.com> | 2013-08-22 00:14:24 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2013-08-22 00:14:24 +0000 |
| commit | 6a7a727174830d448cfcede4090ab7edc3b6d19a (patch) | |
| tree | 83d8cf956694ae836c084b63776d0a56e53d18fc /llvm/lib | |
| parent | b4fae7c3d036da77f63c67d4453ac6df241f2af2 (diff) | |
| download | bcm5719-llvm-6a7a727174830d448cfcede4090ab7edc3b6d19a.tar.gz bcm5719-llvm-6a7a727174830d448cfcede4090ab7edc3b6d19a.zip | |
ARM: R9 is not safe to use for tcGPR.
Indirect tail-calls shouldn't use R9 for the branch destination, as
it's not reliably a call-clobbered register.
rdar://14793425
llvm-svn: 188967
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td index bb7d358ff18..90c6a965acf 100644 --- a/llvm/lib/Target/ARM/ARMRegisterInfo.td +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td @@ -251,7 +251,7 @@ def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>; // to the saved value before the tail call, which would clobber a call address. // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of // this class and the preceding one(!) This is what we want. -def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> { +def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> { let AltOrders = [(and tcGPR, tGPR)]; let AltOrderSelect = [{ return MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only(); |
