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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-08-21 09:09:52 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-08-21 09:09:52 +0000 |
| commit | 41194e3f9ef2f48a16d7013a22dcaea6c5f2e794 (patch) | |
| tree | 6d59de8d05852702c880aaa5e8a38fc995d2188e /llvm/lib | |
| parent | af5f66ac9efee815ccd69653c2adf2f2bb9f7da7 (diff) | |
| download | bcm5719-llvm-41194e3f9ef2f48a16d7013a22dcaea6c5f2e794.tar.gz bcm5719-llvm-41194e3f9ef2f48a16d7013a22dcaea6c5f2e794.zip | |
[mips][msa] Matheus Almeida pointed out a silly mistake in r188893. Fixed it.
I accidentally changed the encoding of the MSA registers to zero instead of 0
to 31. This change restores the encoding the registers had prior to r188893.
This didn't show up in the existing tests because direct-object emission isn't
implemented yet for MSA.
llvm-svn: 188896
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.td b/llvm/lib/Target/Mips/MipsRegisterInfo.td index f2e97b6735c..0e762f23e4a 100644 --- a/llvm/lib/Target/Mips/MipsRegisterInfo.td +++ b/llvm/lib/Target/Mips/MipsRegisterInfo.td @@ -174,7 +174,7 @@ let Namespace = "Mips" in { /// Mips MSA registers /// MSA and FPU cannot both be present unless the FPU has 64-bit registers foreach I = 0-31 in - def W#I : AFPR128<0, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>, + def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>, DwarfRegNum<[!add(I, 32)]>; // Hi/Lo registers |
