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* [X86] Add CLWB to icelake.Craig Topper2017-12-271-1/+2
| | | | | | Per Table 1-1 in October 2017 edition of Intel® Architecture Instruction Set Extensions and Future Features llvm-svn: 321501
* [X86] Reimplement r321437 using custom lowering instead of as a DAG combine.Craig Topper2017-12-271-43/+6
| | | | | | | | My original implementation ran as a DAG combine post type legalization, but it turns out we don't run that DAG combine step if type legalization didn't change anything. Attempts to make the combine run before type legalization as well hit other issues. So just do it in LowerMUL where we can catch more cases. llvm-svn: 321496
* [AArch64] Change order of candidate FMLS patternsMatthew Simpson2017-12-271-22/+22
| | | | | | | | | | | | | | | | | | | | | r319980 added new patterns to the machine combiner for transforming (fsub (fmul x y) z) into (fmla (fneg z) x y). That is, fsub's where the first source operand is an fmul are transformed. We previously only matched the case where the second source operand of an fsub was an fmul, transforming (fsub z (fmul x y)) into (fmls z x y). Now, if we have an fsub where both source operands are fmuls, both of the above patterns are applicable. However, the order in which we add the patterns to the list of candidates determines the transformation that takes place, since only the first pattern that matches will be used. This patch changes the order these two patterns are added to the list of candidates such that we prefer the case where the second source operand is an fmul (the fmls case), rather than the other one (the fmla/fneg case). When both source operands are fmuls, this ordering results in fewer instructions. Differential Revision: https://reviews.llvm.org/D41587 llvm-svn: 321491
* [X86] Fix vmul combine for AVX1 targets.Benjamin Kramer2017-12-271-0/+4
| | | | | | v8i32 is legal von AVX1, but it doesn't have pmuludq for it. llvm-svn: 321490
* [InstCombine] Gracefully handle out of range extractelement indicesSimon Pilgrim2017-12-271-3/+5
| | | | | | | | InstSimplify is responsible for handling these, but we shouldn't just assert here. Reduced from oss-fuzz #4808 test case llvm-svn: 321489
* [DAGCombine] foldBinOpIntoSelect can fail to constant fold in some cases.Simon Pilgrim2017-12-271-6/+8
| | | | | | | | For example, float operations may fail to constant fold under certain circumstances (inf/nan/denormal creation etc.) Reduced from oss-fuzz #4802 test case llvm-svn: 321488
* Improve performance TokenizeWindowsCommandLineRui Ueyama2017-12-271-20/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patcy by Takuto Ikuta. This patch reduces lld link time of chromium's blink_core.dll in component build. Total size of input argument in .directives become nearly 300MB in the build and calling many strchr and assert becomes bottleneck. On my desktop machine, 4 times stats of the link time are like below. Improved around 10%. This patch TotalSeconds : 13.4918885 TotalSeconds : 13.9474257 TotalSeconds : 13.4941082 TotalSeconds : 13.6077962 Avg : 13.63530465 master TotalSeconds : 15.6938531 TotalSeconds : 15.7022508 TotalSeconds : 15.9567202 TotalSeconds : 14.5851505 Avg : 15.48449365 Differential Revision: https://reviews.llvm.org/D41590 llvm-svn: 321479
* [Lint] Don't warn about noalias argument aliasing if other argument is byvalMikael Holmen2017-12-271-2/+10
| | | | | | | | | | | | | | | | | Summary: When using byval, the data is effectively copied as part of the call anyway, so we aren't actually passing the pointer and thus there is no reason to issue a warning. Reviewers: rnk Reviewed By: rnk Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D40118 llvm-svn: 321478
* [SCEV] Be careful with nuw/nsw/exact in InsertBinopSerguei Katkov2017-12-271-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | InsertBinop tries to find an appropriate instruction instead of creating a new instruction. When it checks whether instruction is the same as we need to create it ignores nuw/nsw/exact flags. It leads to invalid behavior when poison instruction can be used when it was not expected. Specifically, for example Expander expands the SCEV built for instruction %a = add i32 %v, 1 It is possible that InsertBinop can find an instruction % b = add nuw nsw i32 %v, 1 and will use it instead of version w/o nuw nsw. It is incorrect. The patch conservatively ignores all instructions with any of poison flags installed. Reviewers: sanjoy, mkazantsev, sebpop, jbhateja Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41576 llvm-svn: 321475
* [SCEV] Do not insert if it is already in cacheSerguei Katkov2017-12-271-2/+10
| | | | | | | | | | | | | | | | | | | This is fix for the crash caused by ScalarEvolution::getTruncateExpr. It expects that if it checked the condition that SCEV is not in UniqueSCEVs cache in the beginning that it will not be there inside this method. However during recursion and transformation/simplification for sub expression, it is possible that these modifications will end up with the same SCEV as we started from. So we must always check whether SCEV is in cache and do not insert item if it is already there. Reviewers: sanjoy, mkazantsev, craig.topper Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41380 llvm-svn: 321472
* [instcombine] add powi(x, 2) -> x * xPhilip Reames2017-12-271-0/+4
| | | | llvm-svn: 321468
* Sink a couple of transforms from instcombine into instsimplify.Philip Reames2017-12-272-24/+28
| | | | llvm-svn: 321467
* [NFC] Extract out a helper function for SimplifyCall(CS, Q)Philip Reames2017-12-272-5/+8
| | | | | | This simplifies code, but the real motivation is that it lets me clean up some downstream code. llvm-svn: 321466
* [Unroll][DebugInfo] Propagate loop body's debug location to epilog preheaderZhaoshi Zheng2017-12-261-1/+6
| | | | | | | NewExit and epilog PreHeader should has the same debug loc as the original loop body, instead of original loop exit. llvm-svn: 321465
* [DAGCombine] visitANDLike - ensure APInt is is in range for ↵Simon Pilgrim2017-12-261-4/+7
| | | | | | | | getSExtValue/getZExtValue Reduced from oss-fuzz #4782 test case llvm-svn: 321464
* [X86] Return SDValue(N, 0) instead of an SDValue() after a successful combine.Craig Topper2017-12-261-2/+2
| | | | | | | | Returning SDValue() means nothing changed, SDValue(N,0) means there was a change but the worklist management was taken care of. I don't know if this has a real effect other than making sure the combine counter in the DAG combiner gets updated, but it is the correct thing to do. llvm-svn: 321463
* [InstCombine] fix miscompile of frem with 0.0 operand (PR34870)Sanjay Patel2017-12-261-4/+0
| | | | | | | We might want to select NAN here or do this transform with fast-math, but this should at least fix the miscompile. llvm-svn: 321461
* It's a fix for Bug 35741 - can't use comments after x86 prefixes.Andrew V. Tischenko2017-12-261-2/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D41579 llvm-svn: 321459
* [ValueTracking] ignore FP signed-zero when detecting a casted-to-integer ↵Sanjay Patel2017-12-261-8/+18
| | | | | | | | | | | | | | | | | fmin/fmax pattern This is a preliminary step for the patch discussed in D41136 (and denoted here with the FIXME comment). When we match an FP min/max that is cast to integer, any intermediate difference between +0.0 or -0.0 should be muted in the result by the conversion (either fptosi or fptoui) of the result. Thus, we can enable 'nsz' for the purpose of matching fmin/fmax. Note that there's probably room to generalize this more, possibly by fixing the current calls to the weak version of isKnownNonZero() in matchSelectPattern() to the more powerful recursive version. Differential Revision: https://reviews.llvm.org/D41333 llvm-svn: 321456
* [DAGCombine] Don't combine (and (setne X, 0), (setne X, -1)) --> (setuge ↵Simon Pilgrim2017-12-261-1/+2
| | | | | | | | (add X, 1), 2) for i1 Reduced from oss-fuzz #4773 test case llvm-svn: 321455
* [InstSimplify] Check for in range extraction index before calling ↵Simon Pilgrim2017-12-261-2/+3
| | | | | | | | APInt::getZExtValue() Reduced from oss-fuzz #4768 test case llvm-svn: 321454
* [X86] Pass itins.rr/itins.rm through properly for some instructions.Craig Topper2017-12-261-11/+12
| | | | llvm-svn: 321452
* [X86] Use SSE_INTMUL_ITINS_P for the AVX-512 MUL instructions to match their ↵Craig Topper2017-12-261-5/+5
| | | | | | SSE/AVX counterparts. llvm-svn: 321451
* [X86] Fix typo in assert message.Craig Topper2017-12-261-1/+1
| | | | llvm-svn: 321450
* [ThinLTO] Don't import functions with noinline attributeEugene Leviant2017-12-251-1/+3
| | | | | | Differential revision: https://reviews.llvm.org/D41489 llvm-svn: 321443
* [MC] - Disallow invalid section groups declarations.George Rimar2017-12-251-2/+2
| | | | | | | | | | | | This fixes parseGroup() so that it always sets error condition on error. Previously it was not done, because parseIdentifier looks never do that, assuming that caller should do it if he wants to. So previously cases from test were silently accepted and produced broken output. Differential revision: https://reviews.llvm.org/D41559 llvm-svn: 321439
* [SafepointIRVerifier] Allow non-dereferencing uses of unrelocated or ↵Max Kazantsev2017-12-251-19/+137
| | | | | | | | | | | | | | | | | | poisoned PHI nodes PHI that has at least one unrelocated input cannot cause any issues by itself, though its uses should be carefully verified. With this patch PHIs are allowed to have any inputs but when all inputs are unrelocated the PHI is marked as unrelocated and if not all inputs are unrelocated then the PHI is marked as poisoned. Poisoned pointers can be used only in three ways: to derive new pointers, in PHIs or in comparisons against constants that are exclusively derived from null. Patch by Daniil Suchkov! Differential Revision: https://reviews.llvm.org/D41006 llvm-svn: 321438
* [X86] Add a DAG combines to turn vXi64 muls into VPMULDQ/VPMULUDQ if the ↵Craig Topper2017-12-251-0/+34
| | | | | | | | | | upper bits are all sign bits or zeros. Normally we catch this during lowering, but vXi64 mul is considered legal when we have AVX512DQ. This DAG combine allows us to avoid PMULLQ with AVX512DQ if we can prove its unnecessary. PMULLQ is 3 uops that take 4 cycles each. While pmuldq/pmuludq is only one 4 cycle uop. llvm-svn: 321437
* [X86] Make some helper methods static functions instead. NFCCraig Topper2017-12-252-19/+15
| | | | llvm-svn: 321433
* [X86] Use SelectionDAG::getFPExtendOrRound to simplify some code.Craig Topper2017-12-251-10/+1
| | | | llvm-svn: 321432
* Make helpers static. No functionality change.Benjamin Kramer2017-12-243-5/+14
| | | | llvm-svn: 321425
* [X86][X87] Mark pseudo memory fold instructions as load/sideeffects ↵Simon Pilgrim2017-12-241-4/+2
| | | | | | | | (PR21160, PR34080, PR34454). Match regular x87 memory fold instructions with load/sideeffects tags, to prevent the schedulers from re-ordering them across the fnstcw/fldcw sequences for truncating stores while they are still pseudo during the stack conversion pass. llvm-svn: 321424
* [X86] Fix (v2f64 (s/uint_to_fp (v2i1))) to avoid scalarization without AVX512DQ.Craig Topper2017-12-241-7/+18
| | | | | | Previously we extended v2i1 to v2f64 and then tried to use cvtuqq2pd/cvtqq2pd, but that only works with avx512dq. So we ended up scalarizing it. Now we widen to v4i1 first and extend to v4i32. llvm-svn: 321420
* [MC] - Teach llvm-mc to handle comdats whose names are numbers.George Rimar2017-12-241-1/+5
| | | | | | | | | | | | | | | Currently llvm-mc ignores COMDATs whose names are numbers, for example following code: .section .foo,"G",@progbits,123,comdat would produce no COMDATs at all. Patch fixes the issue. Differential revision: https://reviews.llvm.org/D41552 llvm-svn: 321419
* [DAGCombiners] Don't turn ANDs to shuffles with zero so early. Give some ↵Craig Topper2017-12-241-7/+8
| | | | | | | | other combines a chance to run. This moves the combine for turning ANDs into shuffle with zero out of SimplifyVBinOps and places it only in visitAND below the reassociate handling. This fixes the specific case I noticed where we failed to combine two ands with constants. llvm-svn: 321417
* [X86] Add assembler predicates to BITALG/VBMI2/VNNI features to be ↵Craig Topper2017-12-241-3/+6
| | | | | | consistent with the other AVX512 ISAs. llvm-svn: 321416
* [X86] Teach WidenMaskArithmetic to handle any constant buildvector on the ↵Craig Topper2017-12-241-10/+5
| | | | | | RHS not just all zeros/ones. llvm-svn: 321415
* [SelectionDAG] Teach SelectionDAG::getNode to constant fold zext/aext/sext ↵Craig Topper2017-12-231-0/+3
| | | | | | of constant build vectors. llvm-svn: 321414
* [CallSiteSplitting] Remove isOrHeader restriction.Florian Hahn2017-12-231-27/+19
| | | | | | | | | | | By following the single predecessors of the predecessors of the call site, we do not need to restrict the control flow. Reviewed By: junbuml, davide Differential Revision: https://reviews.llvm.org/D40729 llvm-svn: 321413
* [X86] Remove type restrictions from WidenMaskArithmetic.Craig Topper2017-12-231-7/+6
| | | | | | This can help AVX-512 code where mask types are legal allowing us to remove extends and truncates to/from mask types. llvm-svn: 321408
* [X86] In WidenMaskArithmetic, make sure we check the input type of a ↵Craig Topper2017-12-231-1/+2
| | | | | | | | truncate on N1. Later in the code we explicitly bypass the truncate so we should be checking its type to make sure that it's safe. llvm-svn: 321407
* [X86] Remove unneeded EVT variable. NFCCraig Topper2017-12-231-6/+5
| | | | | | | | Immediately after it is created we check if its equal to another EVT. Then we inconsistently use one or the other variables in the code below. Instead do the equality check directly on the getValueType result and remove the variable. Use the origina VT variable throughout the remaining code. llvm-svn: 321406
* [X86][X87] Wrap FpI_ pseudo to use PseudoI. NFCI.Simon Pilgrim2017-12-231-2/+1
| | | | llvm-svn: 321405
* [SCCP] Manually fold branches on undef.Davide Italiano2017-12-231-3/+26
| | | | | | | | | | | | | | | This code was originally removed and replace with an assertion because believed unnecessary. It turns out there was simply no test coverage for this case, and the constant folder doesn't yet know about patterns like `br undef %label1, %label2`. Presumably at some point the constant folder might learn about these patterns, but it's a broader change. A testcase will be added to make sure this doesn't regress again in the future. Fixes PR35723. llvm-svn: 321402
* [X86] Add default InstrItinClass to PseudoISimon Pilgrim2017-12-231-2/+3
| | | | | | This will be used to help tidyup existing pseudos that we've added scheduling info to. llvm-svn: 321401
* [X86] Pass the right VT to the getZeroExtendInReg introduced in r321398Craig Topper2017-12-231-1/+1
| | | | | | Apparently we don't have tests for this which I didn't realize before. I'll try to fix that but wanted to fix the obvious bug. llvm-svn: 321399
* [X86] Use SelectionDAG::getZeroExtendInReg instead of implementing it manually.Craig Topper2017-12-231-9/+3
| | | | llvm-svn: 321398
* [SelectionDAG][X86] Don't use ->getValueType(0) after a call to getOperand ↵Craig Topper2017-12-234-14/+14
| | | | | | | | | | to get the type of the operand. getOperand returns an SDValue that contains the node and the result number. There is no guarantee that the result number if 0. By using the -> operator we are calling SDNode::getValueType rather than SDValue::getValueType. This requires supplying a result number and we shouldn't assume it was 0. I don't have a test case. Just noticed while cleaning up some other code and saw that it occurred in other places. llvm-svn: 321397
* [DAG] Add missing case check from findbaseoffset merge from r321389.Nirav Dave2017-12-221-2/+4
| | | | llvm-svn: 321391
* Integrate findBaseOffset address analyses to BaseIndexOffset. NFCI.Nirav Dave2017-12-222-70/+27
| | | | | | | | | BaseIndexOffset supercedes findBaseOffset analysis save only Constant Pool addresses. Migrate analysis to BaseIndexOffset. Relanding after correcting base address matching check. llvm-svn: 321389
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