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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2017-12-27 13:31:50 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2017-12-27 13:31:50 +0000 |
| commit | 293f34301eb3409534fd83b71e40f7e0cc8d252c (patch) | |
| tree | 35679a3521b6a10f4f83d0a5167aaeb453fe1e96 /llvm/lib | |
| parent | e7d032f1d86cded3161bd38e3ed0e0eadb3742f7 (diff) | |
| download | bcm5719-llvm-293f34301eb3409534fd83b71e40f7e0cc8d252c.tar.gz bcm5719-llvm-293f34301eb3409534fd83b71e40f7e0cc8d252c.zip | |
[X86] Fix vmul combine for AVX1 targets.
v8i32 is legal von AVX1, but it doesn't have pmuludq for it.
llvm-svn: 321490
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index ae5100e9bb4..7d2bfd421e4 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -32431,6 +32431,10 @@ static SDValue combineVMUL(SDNode *N, SelectionDAG &DAG, if (VT.getScalarType() != MVT::i64) return SDValue(); + // Don't try to lower 256 bit integer vectors on AVX1 targets. + if (!Subtarget.hasAVX2() && VT.getVectorNumElements() > 2) + return SDValue(); + MVT MulVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2); SDValue LHS = N->getOperand(0); |
