summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* [X86][AVX] Renamed VPERMILPI shuffle comment macros to be more specificSimon Pilgrim2016-07-031-27/+27
| | | | llvm-svn: 274467
* [X86][AVX512] Add support for VPALIGNR/PSHUFD/PSHUFHW/PSHUFLW masked shuffle ↵Simon Pilgrim2016-07-031-0/+16
| | | | | | comments llvm-svn: 274466
* [InstCombine] enable vector select of bools -> logic foldsSanjay Patel2016-07-031-5/+8
| | | | llvm-svn: 274465
* [X86][AVX512] Add support for UNPCK masked shuffle commentsSimon Pilgrim2016-07-031-1/+51
| | | | llvm-svn: 274464
* fix formatting; NFCSanjay Patel2016-07-031-6/+6
| | | | llvm-svn: 274463
* [X86][AVX512] Add support for VPERM/VSHUF masked shuffle commentsSimon Pilgrim2016-07-031-0/+56
| | | | llvm-svn: 274462
* [X86][AVX512] Add support for PMOVZX masked shuffle commentsSimon Pilgrim2016-07-031-0/+34
| | | | llvm-svn: 274461
* [X86][AVX512] Add support for masked shuffle commentsSimon Pilgrim2016-07-031-2/+53
| | | | | | | | | | This patch adds support for including the avx512 mask register information in the mask/maskz versions of shuffle instruction comments. This initial version just adds support for MOVDDUP/MOVSHDUP/MOVSLDUP to reduce the mass of test regenerations, other shuffle instructions can be added in due course. Differential Revision: http://reviews.llvm.org/D21953 llvm-svn: 274459
* [X86][AVX512] Add support for lowering shuffles to VPERMILPSSimon Pilgrim2016-07-031-0/+4
| | | | llvm-svn: 274458
* PR28400: Partly undo r274440 to bring test-suite back to life with the new PMSean Silva2016-07-031-1/+2
| | | | | | | | | PR28400 seems to be not an isolated issue, but a general problem related to caching analyses. We will need to discuss on llvm-dev. A test case is in the PR. llvm-svn: 274457
* [PM] Some preparatory refactoring to minimize the diff of D21921Sean Silva2016-07-031-14/+20
| | | | llvm-svn: 274456
* Remove dead TLI arg of isKnownNonNull and propagate deadness. NFC.Sean Silva2016-07-026-57/+34
| | | | | | | | | | | | | | This actually uncovered a surprisingly large chain of ultimately unused TLI args. From what I can gather, this argument is a remnant of when isKnownNonNull would look at the TLI directly. The current approach seems to be that InferFunctionAttrs runs early in the pipeline and uses TLI to annotate the TLI-dependent non-null information as return attributes. This also removes the dependence of functionattrs on TLI altogether. llvm-svn: 274455
* [PM] Port LoopAccessInfo analysis to new PMXinliang David Li2016-07-023-0/+31
| | | | | | | It is implemented as a LoopAnalysis pass as discussed and agreed upon. llvm-svn: 274452
* Fix spelling.Simon Pilgrim2016-07-021-2/+2
| | | | llvm-svn: 274451
* [X86][AVX512] Add support for lowering shuffles to VPERMILPDSimon Pilgrim2016-07-021-0/+11
| | | | llvm-svn: 274450
* [PM] Some preparatory refactoring to minimize the diff of D21921Sean Silva2016-07-021-15/+17
| | | | | | The main change here is just moving stuff to static functions. llvm-svn: 274446
* [PM] Preparatory cleanups to ArgumentPromotion.Sean Silva2016-07-021-54/+74
| | | | | | | This pulls some obvious changes out of http://reviews.llvm.org/D21921 to minimize the diff. llvm-svn: 274445
* [X86][AVX512] Add support for 512-bit PSHUFB loweringSimon Pilgrim2016-07-021-2/+7
| | | | llvm-svn: 274444
* [X86][AVX512] Converted the MOVDDUP/MOVSLDUP/MOVSHDUP masked intrinsics to ↵Simon Pilgrim2016-07-021-18/+0
| | | | | | generic IR llvm-svn: 274443
* [PM] Fix a small typo from when I ported JumpThreadingSean Silva2016-07-021-1/+1
| | | | llvm-svn: 274440
* [X86][AVX512] Autoupgrade the MOVDDUP/MOVSLDUP/MOVSHDUP intrinsicsSimon Pilgrim2016-07-021-0/+25
| | | | llvm-svn: 274439
* [DIBuilder] Remove dead code. NFC.Benjamin Kramer2016-07-021-34/+0
| | | | llvm-svn: 274438
* [Hexagon] Create global std::map lazily.Benjamin Kramer2016-07-021-3/+3
| | | | | | | | This could of course be a simple binary search with no global state involved at all if someone cares enough. Just don't make everyone linking the hexagon backend pay for it on process startup and shutdown. llvm-svn: 274437
* [X86][AVX512] Add support for lowering shuffles to MOVDDUP/MOVSLDUP/MOVSHDUPSimon Pilgrim2016-07-021-0/+19
| | | | llvm-svn: 274436
* Use arrays or initializer lists to feed ArrayRefs instead of SmallVector ↵Benjamin Kramer2016-07-029-55/+28
| | | | | | | | where possible. No functionality change intended. llvm-svn: 274431
* [esan|cfrag] Add counters for struct array accessesQin Zhao2016-07-021-34/+87
| | | | | | | | | | | | | | | | | Summary: Adds one counter to the struct counter array for counting struct array accesses. Adds instrumentation to insert counter update for struct array accesses. Reviewers: aizatsky Subscribers: llvm-commits, bruening, eugenis, kcc, zhaoqin, vitalybuka Differential Revision: http://reviews.llvm.org/D21594 llvm-svn: 274420
* [SystemZ] Move misplaced SystemZ::TDC to non-memory opcode range.Marcin Koscielnicki2016-07-022-7/+7
| | | | llvm-svn: 274417
* Add RenderScript ArchTypePirama Arumuga Nainar2016-07-021-73/+91
| | | | | | | | | | | | | | | | Summary: Add renderscript32 and renderscript64 ArchTypes. This is to configure the ABI requirement on 32-bit RenderScript that 'long' types have 64-bit size and alignment. 64-bit RenderScript is the same as AArch64, but is added here for completeness. Reviewers: echristo, rsmith Subscribers: aemerson, jfb, rampitec, dschuff, mehdi_amini, llvm-commits, srhines Differential Revision: http://reviews.llvm.org/D21333 llvm-svn: 274412
* [PM] Port ConstantHoisting to the new Pass ManagerMichael Kuperstein2016-07-024-135/+56
| | | | | | Differential Revision: http://reviews.llvm.org/D21945 llvm-svn: 274411
* [codeview] Set the Nested and Scoped ClassOptions based on the scope chainReid Kleckner2016-07-021-12/+31
| | | | | | These are set on both the declaration record and the definition record. llvm-svn: 274410
* LoadStoreVectorizer: Fix warning about extra semicolonMatt Arsenault2016-07-011-2/+2
| | | | llvm-svn: 274406
* TII: Fix inlineasm size counting comments as instsMatt Arsenault2016-07-011-7/+11
| | | | | | | The main problem was counting comments on their own line as instructions. llvm-svn: 274405
* PeepholeOptimizer: Relax assertMatt Arsenault2016-07-011-2/+4
| | | | | | Allow implicit defs llvm-svn: 274402
* [CodeView] Include the offset of nested membersDavid Majnemer2016-07-011-4/+5
| | | | | | | | | | | | | Given something like: struct S { int a; struct { int b; }; }; We would fail to give 'b' offset 4. Instead, we would give it the offset it has inside of it's struct. llvm-svn: 274400
* [CodeView] Pretty print anonymous scopesDavid Majnemer2016-07-011-14/+31
| | | | | | | | A namespace without a name should be written out as `anonymous namespace' while a tag type without a name should be written out as <unnamed-tag>. llvm-svn: 274399
* AMDGPU: Add feature for unaligned accessMatt Arsenault2016-07-015-12/+32
| | | | llvm-svn: 274398
* AMDGPU: Expand unaligned accesses earlyMatt Arsenault2016-07-012-21/+48
| | | | | | | | Due to visit order problems, in the case of an unaligned copy the legalized DAG fails to eliminate extra instructions introduced by the expansion of both unaligned parts. llvm-svn: 274397
* [msan] Fix __msan_maybe_ for non-standard type sizes.Evgeniy Stepanov2016-07-011-1/+1
| | | | | | | | | | | Fix incorrect calculation of the type size for __msan_maybe_warning_N call that resulted in an invalid (narrowing) zext instruction and "Assertion `castIsValid(op, S, Ty) && "Invalid cast!"' failed." Only happens in very large functions (with more than 3500 MSan checks) operating on integer types that are not power-of-two. llvm-svn: 274395
* AMDGPU: Improve load/store of illegal types.Matt Arsenault2016-07-013-113/+102
| | | | | | | | | | There was a combine before to handle the simple copy case. Split this into handling loads and stores separately. We might want to change how this handles some of the vector extloads, since this can result in large code size increases. llvm-svn: 274394
* [codeview] Don't record UDTs for anonymous structsReid Kleckner2016-07-011-0/+4
| | | | | | | | MSVC makes up names for these anonymous structs, but we don't (yet). Eventually Clang should use getTypedefNameForAnonDecl() to put some name in the debug info, and we can update the test case when that happens. llvm-svn: 274391
* Address two correctness issues in LoadStoreVectorizerAlina Sbirlea2016-07-011-3/+10
| | | | | | | | | | | | | | Summary: GetBoundryInstruction returns the last instruction as the instruction which follows or end(). Otherwise the last instruction in the boundry set is not being tested by isVectorizable(). Partially solve reordering of instructions. More extensive solution to follow. Reviewers: tstellarAMD, llvm-commits, jlebar Subscribers: escha, arsenm, mzolotukhin Differential Revision: http://reviews.llvm.org/D21934 llvm-svn: 274389
* [Hexagon] Revert r274381: that was actually wrongKrzysztof Parzyszek2016-07-011-1/+1
| | | | llvm-svn: 274384
* [Hexagon] Use MachineOperand::readsReg instead of isUseKrzysztof Parzyszek2016-07-011-1/+1
| | | | llvm-svn: 274381
* [pdb] Check the display name for <unnamed-tag>, not the linkage nameReid Kleckner2016-07-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This issue was encountered on libcmt.pdb, which has a type record that looks like this: Struct (0x1094) { TypeLeafKind: LF_STRUCTURE (0x1505) MemberCount: 3 Properties [ (0x200) HasUniqueName (0x200) ] FieldList: <field list> (0x1093) DerivedFrom: 0x0 VShape: 0x0 SizeOf: 4 Name: <unnamed-tag> LinkageName: .?AU<unnamed-tag>@@ } The checks for startswith/endswith "<unnamed-tag>" should look at the display name, not the linkage name. llvm-svn: 274376
* [codeview] Assert that our CV type records are validReid Kleckner2016-07-011-3/+27
| | | | | | | | | | | We were asserting that our type records were valid when emitting assembly, but not when emitting an object file. I've been seeing lots of LNK1285 errors (corrupt PDB) during incremental debug self-host builds with the MSVC linker, and hopefully this will catch some of them earlier. llvm-svn: 274373
* AMDGPU/SI: Enable testing several variants for si schedulerMatt Arsenault2016-07-011-2/+2
| | | | | | | | | | Enable testing different scheduling variants if sgpr usage is very high. It was previously disabled because of a bug in handleMove, but it has been fixed since. Patch by Axel Davy llvm-svn: 274372
* Revert r274347 "[ARM] Refactor Thumb2 mul instruction descs"Hans Wennborg2016-07-011-144/+327
| | | | | | This caused PR28387: Assertion "#operands for dag node doesn't match .td file!" llvm-svn: 274367
* CodeGen: Use MachineInstr& in RegisterCoalescer, NFCDuncan P. N. Exon Smith2016-07-011-38/+37
| | | | | | | Remove a few more implicit iterator to pointer conversions by preferring MachineInstr&. llvm-svn: 274363
* fix documentation comments; NFCSanjay Patel2016-07-011-13/+12
| | | | llvm-svn: 274362
* CodeGen: Avoid implicit conversions in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-07-011-2/+2
| | | | | | | Avoid implicit conversions from MachineBasicBlock::iterator to MachineInstr* in TargetInstrInfo. llvm-svn: 274361
OpenPOWER on IntegriCloud