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author | Marcin Koscielnicki <koriakin@0x04.net> | 2016-07-02 02:20:40 +0000 |
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committer | Marcin Koscielnicki <koriakin@0x04.net> | 2016-07-02 02:20:40 +0000 |
commit | 32e8734e41722ed0a7c034deb274714340d43646 (patch) | |
tree | c97bd73c422f204f668fddcf6f9f53d281598cad /llvm/lib | |
parent | d9b9009c611a03b47b40f780de5562b141810682 (diff) | |
download | bcm5719-llvm-32e8734e41722ed0a7c034deb274714340d43646.tar.gz bcm5719-llvm-32e8734e41722ed0a7c034deb274714340d43646.zip |
[SystemZ] Move misplaced SystemZ::TDC to non-memory opcode range.
llvm-svn: 274417
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 2 | ||||
-rw-r--r-- | llvm/lib/Target/SystemZ/SystemZISelLowering.h | 12 |
2 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 8535f7a201f..70bae07035d 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -4670,6 +4670,7 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(VISTR_CC); OPCODE(VSTRC_CC); OPCODE(VSTRCZ_CC); + OPCODE(TDC); OPCODE(ATOMIC_SWAPW); OPCODE(ATOMIC_LOADW_ADD); OPCODE(ATOMIC_LOADW_SUB); @@ -4684,7 +4685,6 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(ATOMIC_CMP_SWAPW); OPCODE(LRV); OPCODE(STRV); - OPCODE(TDC); OPCODE(PREFETCH); } return nullptr; diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h index f5a42f09222..8d21f2282b4 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h @@ -278,6 +278,12 @@ enum NodeType : unsigned { VSTRC_CC, VSTRCZ_CC, + // Test Data Class. + // + // Operand 0: the value to test + // Operand 1: the bit mask + TDC, + // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or // ATOMIC_LOAD_<op>. // @@ -324,12 +330,6 @@ enum NodeType : unsigned { // Operand 2: the type of store (i16, i32, i64) STRV, - // Test Data Class. - // - // Operand 0: the value to test - // Operand 1: the bit mask - TDC, - // Prefetch from the second operand using the 4-bit control code in // the first operand. The code is 1 for a load prefetch and 2 for // a store prefetch. |