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* [AArch64] Enable rematerialization of float 0 values.Chad Rosier2015-03-231-2/+9
| | | | | | Patch by Geoff Berry<gberry@codeaurora.org>. llvm-svn: 232967
* Revert "[ARM] Add more pattern matching for f16 <-> f64 conversions"Bradley Smith2015-03-231-8/+0
| | | | | | | | | | This change is incorrect since it converts double rounding into single rounding, which can produce different results. Instead this optimization will be done by modifying Clang's codegen to not produce double rounding in the first place. This reverts commit r232954. llvm-svn: 232962
* Simplify boolean expressions with true and false using clang-tidyEli Bendersky2015-03-234-25/+19
| | | | | | | | Patch by Richard (legalize@xmission.com) Differential Revision: http://reviews.llvm.org/D8521 llvm-svn: 232961
* [ARM] Remove target-specific ITOFP/FPTOI nodesJames Molloy2015-03-235-72/+134
| | | | | | | | Anton tried this 5 years ago but it was reverted due to extra VMOVs being emitted. This can be easily fixed with a liberal application of patterns - matching loads/stores and extractelts. llvm-svn: 232958
* R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2015-03-231-2/+10
| | | | | | | This function assumed that SMRD instructions always have immediate offsets, which is not always the case. llvm-svn: 232957
* [Hexagon] Simplify boolean expressionColin LeMahieu2015-03-231-4/+1
| | | | | | | Patch by Richard http://reviews.llvm.org/D8523 llvm-svn: 232955
* [ARM] Add more pattern matching for f16 <-> f64 conversionsBradley Smith2015-03-231-0/+8
| | | | | | | | | | | | | | | Specifically when the conversion is done in two steps, f16 -> f32 -> f64. For example: %1 = tail call float @llvm.convert.from.fp16.f32(i16 %0) %conv = fpext float %1 to double to: vcvtb.f64.f16 llvm-svn: 232954
* [gcov] Move formatBranchInfo into an anonymous namespace.Benjamin Kramer2015-03-231-1/+1
| | | | | | NFC. llvm-svn: 232949
* Move private classes into anonymous namespacesBenjamin Kramer2015-03-236-0/+12
| | | | | | NFC. llvm-svn: 232944
* Fix sign extension for MIPS64 in makeLibCall functionPetar Jovanovic2015-03-233-3/+15
| | | | | | | | | | | | Fixing sign extension in makeLibCall for MIPS64. In MIPS64 architecture all 32 bit arguments (int, unsigned int, float 32 (soft float)) must be sign extended. This fixes test "MultiSource/Applications/oggenc/". Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D7791 llvm-svn: 232943
* [aarch64] Distinguish the 'Q' and 'm' inline assembly memory constraints.Daniel Sanders2015-03-232-9/+19
| | | | | | | | | | | | | | | | | | | | Summary: But still handle them the same way since I don't know how they differ on this target. Clang also has code for 'Ump', 'Utf', 'Usa', and 'Ush' but calls llvm_unreachable() on this code path so they are not converted to a constraint id at the moment. No functional change intended. Reviewers: t.p.northover Subscribers: aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D8177 llvm-svn: 232941
* [SDAG] Don't widen VSETCC during type legalization for split operandsHal Finkel2015-03-231-0/+10
| | | | | | | | | | | | Because the operands of a vector SETCC node can be of a different type from the result (and often are), it can happen that even if we'd prefer to widen the result type of the SETCC, the operands have been split instead. In this case, the SETCC result also must be split. This mirrors what is done in WidenVecRes_SELECT, and should be NFC elsewhere because if the operands are not widened the following calls to GetWidenedVector will assert (which is what was happening in the test case). llvm-svn: 232935
* Fix typo 'AVX too' instead of 'AVX2'Craig Topper2015-03-231-2/+2
| | | | llvm-svn: 232929
* [X86] Add one stepping of Broadwell to the CPU name autodetection for ↵Craig Topper2015-03-231-0/+6
| | | | | | march=native. llvm-svn: 232927
* Silence a GCC warningDavid Majnemer2015-03-221-2/+2
| | | | llvm-svn: 232923
* FoldingSet: Make FoldingSetImpl's dtor protected and non-virtualBenjamin Kramer2015-03-221-0/+2
| | | | | | | | | It's not intended to be polymorphically deleted. Make FoldingSet and ContextualFoldingSet final to avoid noise from -Wnon-virtual-dtor. No functional change intended. llvm-svn: 232922
* Fixed MSVC compile warning issue introduced in r232837Simon Pilgrim2015-03-221-1/+2
| | | | | | - was reporting 'warning C4715: 'getType32' : not all control paths return a value' llvm-svn: 232913
* [SimplifyLibCalls] Fix negative shifts being produced by the memchr -> ↵Benjamin Kramer2015-03-211-1/+3
| | | | | | bitfield transform. llvm-svn: 232903
* [SimplifyLibCalls] Turn memchr(const, C, const) into a bitfield check.Benjamin Kramer2015-03-212-5/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | strchr("123!", C) != nullptr is a common pattern to check if C is one of 1, 2, 3 or !. If the largest element of the string is smaller than the target's register size we can easily create a bitfield and just do a simple test for set membership. int foo(char C) { return strchr("123!", C) != nullptr; } now becomes cmpl $64, %edi ## range check sbbb %al, %al movabsq $0xE000200000001, %rcx btq %rdi, %rcx ## bit test sbbb %cl, %cl andb %al, %cl ## and the two conditions andb $1, %cl movzbl %cl, %eax ## returning an int ret (imho the backend should expand this into a series of branches, but that's a different story) The code is currently limited to bit fields that fit in a register, so usually 64 or 32 bits. Sadly, this misses anything using alpha chars or {}. This could be fixed by just emitting a i128 bit field, but that can generate really ugly code so we have to find a better way. To some degree this is also recreating switch lowering logic, but we can't simply emit a switch instruction and thus change the CFG within instcombine. llvm-svn: 232902
* SimplifyLibCalls: Add basic optimization of memchr calls.Benjamin Kramer2015-03-211-0/+40
| | | | | | This is just memchr(x, y, 0) -> nullptr and constant folding. llvm-svn: 232896
* ValueTracking: Forward getConstantStringInfo's TrimAtNul param into ↵Benjamin Kramer2015-03-211-2/+3
| | | | | | | | | | | recursive invocation Currently this is only used to tweak the backend's memcpy inlining heuristics, testing that isn't very helpful. A real test case will follow in the next commit, where this behavior would cause a real miscompilation. llvm-svn: 232895
* MemoryDependenceAnalysis: Don't miscompile atomicsDavid Majnemer2015-03-211-11/+4
| | | | | | | | | | | | r216771 introduced a change to MemoryDependenceAnalysis that allowed it to reason about acquire/release operations. However, this change does not ensure that the acquire/release operations pair. Unfortunately, this leads to miscompiles as we won't see an acquire load as properly memory effecting. This largely reverts r216771. This fixes PR22708. llvm-svn: 232889
* Remove the target independent TargetMachine::getSubtarget andEric Christopher2015-03-2111-18/+24
| | | | | | | | | | | | | | | | | | | TargetMachine::getSubtargetImpl routines. This keeps the target independent code free of bare subtarget calls while the remainder of the backends are migrated, or not if they don't wish to support per-function subtargets as would be needed for function multiversioning or LTO of disparate cpu subarchitecture types, e.g. clang -msse4.2 -c foo.c -emit-llvm -o foo.bc clang -c bar.c -emit-llvm -o bar.bc llvm-link foo.bc bar.bc -o baz.bc llc baz.bc and get appropriate code for what the command lines requested. llvm-svn: 232885
* Remove the bare getSubtargetImpl call from the AArch64 port. As partEric Christopher2015-03-212-6/+0
| | | | | | | of this add a test that shows we can generate code for functions that specifically enable a subtarget feature. llvm-svn: 232884
* Remove the bare getSubtargetImpl call from the PPC port. As partEric Christopher2015-03-212-5/+1
| | | | | | | of this add a test that shows we can generate code with for functions that differ by subtarget feature. llvm-svn: 232882
* Grab a subtarget off of an AMDGPUTargetMachine rather than aEric Christopher2015-03-211-11/+11
| | | | | | | bare target machine in preparation for the TargetMachine bare getSubtarget/getSubtargetImpl calls going away. llvm-svn: 232880
* Cache the Function dependent subtarget on the MachineFunction.Eric Christopher2015-03-212-2/+1
| | | | | | | | | | | As preparation for removing the getSubtargetImpl() call from TargetMachine go ahead and flip the switch on caching the function dependent subtarget and remove the bare getSubtargetImpl call from the X86 port. As part of this add a few tests that show we can generate code and assemble on X86 based on features/cpu on the Function. llvm-svn: 232879
* Grab the cached subtarget off of the MachineFunction.Eric Christopher2015-03-211-5/+4
| | | | llvm-svn: 232878
* Grab a subtarget off of a MipsTargetMachine rather than aEric Christopher2015-03-212-7/+11
| | | | | | | bare target machine in preparation for the TargetMachine bare getSubtarget/getSubtargetImpl calls going away. llvm-svn: 232877
* Simplify the query for a subtarget in the NVPTX pass manager.Eric Christopher2015-03-211-2/+1
| | | | llvm-svn: 232876
* Change getISAEncoding to use the target triple to determineEric Christopher2015-03-212-5/+7
| | | | | | | | thumb-ness similar to the rest of the Module level asm printing infrastructure as debug info finalization happens after the function may be missing. llvm-svn: 232875
* Make the Hexagon ISelDAGToDAG pass set the subtarget dynamicallyEric Christopher2015-03-212-12/+19
| | | | | | on each runOnMachineFunction invocation. llvm-svn: 232874
* [sanitizer] experimental tracing for cmp instructionsKostya Serebryany2015-03-211-13/+50
| | | | llvm-svn: 232873
* [CodeGen][IfCvt] Don't re-ifcvt blocks with unanalyzable terminators.Ahmed Bougacha2015-03-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we couldn't analyze its terminator (i.e., it's an indirectbr, or some other weirdness), we can't safely re-if-convert a predicated block, because we can't tell whether the predicated terminator can fallthrough (it does). Currently, we would completely ignore the fallthrough successor. In the added testcase, this means we used to generate: ... @ %entry: cmp r5, #21 ittt ne @ %cc1f: cmpne r7, #42 @ %cc2t: strne.w r5, [r8] movne pc, r10 @ %cc1t: ... Whereas the successor of %cc1f was originally %bb1. With the fix, we get the correct: ... @ %entry: cmp r5, #21 itt eq @ %cc1t: streq.w r5, [r11] moveq pc, r0 @ %cc1f: cmp r7, #42 itt ne @ %cc2t: strne.w r5, [r8] movne pc, r10 @ %bb1: ... rdar://20192768 Differential Revision: http://reviews.llvm.org/D8509 llvm-svn: 232872
* [AArch64] Prefer UZP for concat_vector of illegal truncs.Ahmed Bougacha2015-03-211-16/+12
| | | | | | Follow-up to r232459: prefer a UZP shuffle to the intermediate truncs. llvm-svn: 232871
* Make getLastArgNoClaim work for up to 4 arguments.Filipe Cabecinhas2015-03-201-0/+20
| | | | | | | | | | | | | | Summary: This is needed for http://reviews.llvm.org/D8507 I have no idea what stand-alone tests could be done, if needed. Reviewers: Bigcheese, craig.topper, samsonov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8508 llvm-svn: 232859
* [X86, AVX] instcombine common cases of vperm2* intrinsics into shufflesSanjay Patel2015-03-201-0/+59
| | | | | | | | | | | | | | | | | | | | vperm2* intrinsics are just shuffles. In a few special cases, they're not even shuffles. Optimizing intrinsics in InstCombine is better than handling this in the front-end for at least two reasons: 1. Optimizing custom-written SSE intrinsic code at -O0 makes vector coders really angry (and so I have regrets about some patches from last week). 2. Doing mask conversion logic in header files is hard to write and subsequently read. There are a couple of TODOs in this patch to complete this optimization. Differential Revision: http://reviews.llvm.org/D8486 llvm-svn: 232852
* Fixing a bug with WinEH PHI handlingAndrew Kaylor2015-03-202-5/+30
| | | | llvm-svn: 232851
* [X86] Prefer blendps over insertps codegen for one special caseSanjay Patel2015-03-201-9/+22
| | | | | | | | | | | | | | | | | | | | With this patch, for this one exact case, we'll generate: blendps %xmm0, %xmm1, $1 instead of: insertps %xmm0, %xmm1, $0 If there's a memory operand available for load folding and we're optimizing for size, we'll still generate the insertps. The detailed performance data motivation for this may be found in D7866; in summary, blendps has 2-3x throughput vs. insertps on widely used chips. Differential Revision: http://reviews.llvm.org/D8332 llvm-svn: 232850
* X86: Make helper functions static. NFC.Benjamin Kramer2015-03-201-4/+4
| | | | llvm-svn: 232848
* Remove dead calls and function arguments dealing with TRI in StackMaps.Eric Christopher2015-03-201-4/+2
| | | | llvm-svn: 232847
* Don't declare all text sections at the start of the .sRafael Espindola2015-03-206-72/+61
| | | | | | | | | | | | | | | | | The code this patch removes was there to make sure the text sections went before the dwarf sections. That is necessary because MachO uses offsets relative to the start of the file, so adding a section can change relaxations. The dwarf sections were being printed at the start just to produce symbols pointing at the start of those sections. The underlying issue was fixed in r231898. The dwarf sections are now printed when they are about to be used, which is after we printed the text sections. To make sure we don't regress, the patch makes the MachO streamer assert if CodeGen puts anything unexpected after the DWARF sections. llvm-svn: 232842
* AsmPrinter: Check subprogram before using itDuncan P. N. Exon Smith2015-03-201-2/+5
| | | | | | | Check return of `getDISubprogram()` before using it. A WIP patch makes `DIDescriptor` accessors more strict (and would crash on this). llvm-svn: 232838
* Reorganize the x86 ELF relocation selection logic.Rafael Espindola2015-03-201-176/+198
| | | | | | | | | | | | | | | The main differences are: * Split in 32 and 64 bit functions. * First switch on the Modifier so that we have only one non fully covered switch. * Map the fixup kind first to a x86_64 (or i386) specific enum, to make it easy to handle cases like X86::reloc_riprel_4byte_movq_load. * Switch on IsPCRel last, which reduces code duplication. Fixes pr22308. llvm-svn: 232837
* DwarfDebug: Check for null DebugLocsDuncan P. N. Exon Smith2015-03-201-13/+15
| | | | | | | | | | `DL` might be null, so check for that before using accessors. A WIP patch to make `DIDescriptors` more strict fails otherwise. As a bonus, I think the logic is easier to follow now (despite the extra nesting depth). llvm-svn: 232836
* Verifier: Check that !dbg attachments have the right typeDuncan P. N. Exon Smith2015-03-201-0/+7
| | | | | | | | | | | | | | | A WIP patch makes `DIDescriptor` accessors more strict, which in turn causes the `DebugInfoFinder` to crash on wrongly typed `!dbg` attachments. Catch that error up front in `Verifier::visitInstruction()`. Also remove a test that we "handle" invalid `!dbg` attachments, added back in r99938. We don't want to handle those anymore. Note: I'm *not* recursing and verifying the debug info graph reachable from this node; that work is already done by `verifyDebugInfo()`. llvm-svn: 232834
* DebugInfoFinder: Check for null imported entitiesDuncan P. N. Exon Smith2015-03-201-0/+2
| | | | | | | | Don't use the accessors in `DIImportedEntity` on a null pointer. (A WIP patch to make `DIDescriptor` accessors more strict crashes here otherwise.) llvm-svn: 232833
* SanitizerCoverage: Check for null DebugLocsDuncan P. N. Exon Smith2015-03-201-2/+3
| | | | | | | After a WIP patch to make `DIDescriptor` accessors more strict, this started asserting. llvm-svn: 232832
* SelectionDAGBuilder: Rangeify a loop. NFC.Hans Wennborg2015-03-201-8/+6
| | | | llvm-svn: 232831
* SelectionDAGBuilder::handleJTSwitchCase, simplify loop; NFCHans Wennborg2015-03-201-9/+4
| | | | llvm-svn: 232830
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