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authorDaniel Sanders <daniel.sanders@imgtec.com>2015-03-23 11:33:15 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2015-03-23 11:33:15 +0000
commitf731eee322021c006d5cdccbfbaffcc474cceb89 (patch)
treebd5790dc0609af1d630391300f1cf221ef111e12 /llvm/lib
parent3205f521985dc6c53c3d1db0eb5b164fff85156c (diff)
downloadbcm5719-llvm-f731eee322021c006d5cdccbfbaffcc474cceb89.tar.gz
bcm5719-llvm-f731eee322021c006d5cdccbfbaffcc474cceb89.zip
[aarch64] Distinguish the 'Q' and 'm' inline assembly memory constraints.
Summary: But still handle them the same way since I don't know how they differ on this target. Clang also has code for 'Ump', 'Utf', 'Usa', and 'Ush' but calls llvm_unreachable() on this code path so they are not converted to a constraint id at the moment. No functional change intended. Reviewers: t.p.northover Subscribers: aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D8177 llvm-svn: 232941
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp20
-rw-r--r--llvm/lib/Target/AArch64/AArch64ISelLowering.h8
2 files changed, 19 insertions, 9 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index f401b70e0f8..44d20fcfd84 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -212,13 +212,19 @@ static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
- assert(ConstraintID == InlineAsm::Constraint_m &&
- "unexpected asm memory constraint");
- // Require the address to be in a register. That is safe for all AArch64
- // variants and it is hard to do anything much smarter without knowing
- // how the operand is used.
- OutOps.push_back(Op);
- return false;
+ switch(ConstraintID) {
+ default:
+ llvm_unreachable("Unexpected asm memory constraint");
+ case InlineAsm::Constraint_i:
+ case InlineAsm::Constraint_m:
+ case InlineAsm::Constraint_Q:
+ // Require the address to be in a register. That is safe for all AArch64
+ // variants and it is hard to do anything much smarter without knowing
+ // how the operand is used.
+ OutOps.push_back(Op);
+ return false;
+ }
+ return true;
}
/// SelectArithImmed - Select an immediate value that can be represented as
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 4d5b619e752..5ff11e86eb9 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -475,8 +475,12 @@ private:
unsigned getInlineAsmMemConstraint(
const std::string &ConstraintCode) const override {
- // FIXME: Map different constraints differently.
- return InlineAsm::Constraint_m;
+ if (ConstraintCode == "Q")
+ return InlineAsm::Constraint_Q;
+ // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
+ // followed by llvm_unreachable so we'll leave them unimplemented in
+ // the backend for now.
+ return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
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