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* Strip trailing whitespace. NFCI.Simon Pilgrim2017-12-101-3/+3
| | | | llvm-svn: 320306
* [X86] Flag ZNVER1 scheduler model as completeSimon Pilgrim2017-12-101-6/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320304
* [X86] Flag SLM scheduler model as completeSimon Pilgrim2017-12-101-5/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320303
* [X86][AVX[ Tag VZEROALL/VZEROUPPER instructions scheduler classesSimon Pilgrim2017-12-102-3/+9
| | | | llvm-svn: 320302
* [X86] Tag SSE4A instructions as SSE INTALU scheduler classesSimon Pilgrim2017-12-101-4/+8
| | | | llvm-svn: 320301
* [X86] Flag BTVER2 scheduler model as completeSimon Pilgrim2017-12-101-4/+3
| | | | | | We just have to locally tag COPY as WriteMove llvm-svn: 320300
* [X86] Tag ADJSTACK instructions as INTALU scheduler classSimon Pilgrim2017-12-101-11/+9
| | | | llvm-svn: 320299
* [SCEV] Fix wrong Equal predicate created in getAddRecForPhiWithCastsDorit Nuzman2017-12-101-6/+9
| | | | | | | | | | | | | | | | | | | CreateAddRecFromPHIWithCastsImpl() adds an IncrementNUSW overflow predicate which allows the PSCEV rewriter to rewrite this scev expression: (zext i8 {0, + , (trunc i32 step to i8)} to i32) into {0, +, (sext i8 (trunc i32 step to i8) to i32)} But then it adds the wrong Equal predicate: %step == (zext i8 (trunc i32 %step to i8) to i32). instead of: %step == (sext i8 (trunc i32 %step to i8) to i32) This is fixed here. Differential Revision: https://reviews.llvm.org/D40641 llvm-svn: 320298
* [X86] Tag MORESTACK instructions as ret scheduler classSimon Pilgrim2017-12-101-3/+3
| | | | llvm-svn: 320296
* [X86] Fix duplicate entries in skylake server scheduler model by changing ↵Craig Topper2017-12-101-8/+8
| | | | | | | | Z128 to Z256 Based on the fact that the 'Y' version of the instruction is next to this, I assume Z256 is the intended value. llvm-svn: 320295
* [X86] Add MOVQI2PQIrm, MOVSDmr, and MOVSDrm to scheduler informationCraig Topper2017-12-105-0/+15
| | | | | | The VEX versions were present but not the legacy SSE versions. llvm-svn: 320294
* [X86] Add LEA64_32r to scheduler models for ↵Craig Topper2017-12-105-5/+5
| | | | | | Sandybridge,Haswell,Broadwell,Skylake llvm-svn: 320293
* [X86] Add IN16/OUT16 to scheduling information for Haswell,Broadwell,SkylakeCraig Topper2017-12-104-16/+16
| | | | | | Sandy Bridge is also missing it, but it has other issues. See PR35590. llvm-svn: 320292
* [X86] Fix scheduler models to support ADD32ri in addition to ADD32ri8. ↵Craig Topper2017-12-105-80/+80
| | | | | | Similar for all sizes of AND/OR/XOR/SUB/ADC/SBB/CMP. llvm-svn: 320291
* [X86] Rename some instructions so that 'b' is added as a suffix instead of ↵Craig Topper2017-12-103-22/+22
| | | | | | replacing an 'r' llvm-svn: 320290
* [X86] Add CMPSDrr/rm to the scheduler models.Craig Topper2017-12-105-0/+10
| | | | | | Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing. llvm-svn: 320289
* PowerPC: support external pid instructions in MC layer.Tim Northover2017-12-101-0/+57
| | | | | | | | | | | This adds assembly & disassembly support for the e500mc "external pid" instructions. See https://reviews.llvm.org/D39249. Patch by vit9696 <vit9696@avp.su> llvm-svn: 320287
* [PGO] change arg type to uint64_t to match member field typeXinliang David Li2017-12-101-2/+2
| | | | llvm-svn: 320285
* [X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since ↵Craig Topper2017-12-103-20/+20
| | | | | | they can only be selected by intrinsics. llvm-svn: 320283
* [X86] Correct the _Int part of more scheduler model instrexes. Put _b in the ↵Craig Topper2017-12-101-78/+78
| | | | | | correct order relative to _Int llvm-svn: 320282
* [X86] Remove ReadAfterLd from several several rb instructionsCraig Topper2017-12-101-5/+5
| | | | | | | | This affects CVTSD2SS, FMA, RCP28, RSQRT28, and SQRT scalar instructions 'b' here refers to 'sae' not broadcast. These aren't memory instructions. llvm-svn: 320281
* [X86] Fix bad regular expressions in the scheduler models. Question marks ↵Craig Topper2017-12-104-239/+231
| | | | | | | | | | should be outside of multicharacter parenthesized expressions If the question mark is inside the parentheses it only applies to the single character proceeding it. I had to make a few additional cleanups to fix some duplicate warnings that were exposed by fixing this. llvm-svn: 320279
* [X86] Make the _Int part of some instregex sheduler patterns optionalCraig Topper2017-12-101-8/+8
| | | | llvm-svn: 320278
* [X86] Add the commutable floating point min/max pseudo instructions to ↵Craig Topper2017-12-104-160/+160
| | | | | | sandybridge,haswell,broadwell,skylakeclient scheduler models. llvm-svn: 320277
* [X86] Tag PIC setup instruction as jump scheduler classSimon Pilgrim2017-12-101-2/+3
| | | | llvm-svn: 320276
* [X86] Tag ACQUIRE/RELEASE atomic instructions as microcoded scheduler classesSimon Pilgrim2017-12-101-3/+5
| | | | | Note: We may be too pessimistic here and should possibly use something closer to the LOCK arithmetic instructions llvm-svn: 320275
* [X86] Tag TLS instructions as system scheduler classesSimon Pilgrim2017-12-101-1/+2
| | | | llvm-svn: 320274
* [X86] Tag ALLOCA/VAARG instructions as system scheduler classesSimon Pilgrim2017-12-101-0/+2
| | | | llvm-svn: 320273
* [AArch64] Improve loop unrolling performance on Cavium T99Joel Jones2017-12-091-1/+1
| | | | | | | | | | | | | | | | | This patch improves performance on Cavium T99 as shown here (libquantum 0.2.4): https://docs.google.com/spreadsheets/d/1Lo1o2E1NjrpkwS7DvYYWsiVvPdd93h7KBaqeptMrZPY/edit?usp=sharing By increasing the LoopMicroOpsBufferSize in the Cavium T99 Scheduler file, loop unrolling becomes more aggressive. This helps performance on T99. Test case included. Patch by Stefan Teleman Differential Revision: https://reviews.llvm.org/D40695 llvm-svn: 320272
* [InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515)Simon Pilgrim2017-12-091-6/+5
| | | | | | Don't assume that the pattern matched SRL can be cast to an Instruction (might be ConstExpr etc.) llvm-svn: 320270
* Infer lowest bits of an integer Multiply when the low bits of the operands ↵Simon Dardis2017-12-091-9/+66
| | | | | | | | | | | | | | | are known When the lowest bits of the operands to an integer multiply are known, the low bits of the result are deducible. Code to deduce known-zero bottom bits already existed, but this change improves on that by deducing known-ones. Patch by: Pedro Ferreira Reviewers: craig.topper, sanjoy, efriedma Differential Revision: https://reviews.llvm.org/D34029 llvm-svn: 320269
* [X86] Use KMOV instructions to zero upper bits of vectors when possible.Craig Topper2017-12-091-12/+29
| | | | llvm-svn: 320268
* [X86] Improve lowering of vXi1 insert_subvectors to better utilize ↵Craig Topper2017-12-091-67/+87
| | | | | | | | (insert_subvector zero, vec, 0) for zeroing upper bits. This can be better recognized during isel when the producer already zeroed the upper bits. llvm-svn: 320267
* [X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classesSimon Pilgrim2017-12-091-3/+7
| | | | llvm-svn: 320266
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-12-092-13/+13
| | | | llvm-svn: 320265
* [X86] Tag FS/GS BASE R/W instruction scheduler classesSimon Pilgrim2017-12-092-9/+18
| | | | llvm-svn: 320264
* [X86] Tag REP/REPNE prefix instructions as microcoded scheduler classesSimon Pilgrim2017-12-091-3/+2
| | | | llvm-svn: 320263
* [X86] Tag missing EH pseudo instruction scheduler classesSimon Pilgrim2017-12-092-3/+4
| | | | llvm-svn: 320262
* [X86] Tag frame pointer XORs instruction scheduler classesSimon Pilgrim2017-12-091-2/+4
| | | | llvm-svn: 320261
* [X86] Don't use getTargetConstant for all 0s and all 1s mask vector.Craig Topper2017-12-091-10/+8
| | | | llvm-svn: 320260
* [X86] Tag segment prefixes as NOP instruction scheduling classesSimon Pilgrim2017-12-091-7/+8
| | | | llvm-svn: 320257
* [X86][AVX512] Drop a default NoItinerary argument that isn't used any more. ↵Simon Pilgrim2017-12-091-6/+6
| | | | | | | | NFCI. Requires re-ordering of AVX512_maskable_custom arguments. llvm-svn: 320255
* Fix 'enumeral and non-enumeral type in conditional expression' gcc warning. ↵Simon Pilgrim2017-12-091-1/+1
| | | | | | NFCI. llvm-svn: 320254
* Fix signed/unsigned gcc warning. NFCI.Simon Pilgrim2017-12-091-1/+1
| | | | llvm-svn: 320253
* [InlineFunction] Set debug loc for call to forward varargs.Florian Hahn2017-12-091-0/+1
| | | | | | | | | | | | Reviewers: aprantl, dblaikie, rnk Reviewed By: rnk Subscribers: eraman, llvm-commits, JDevlieghere Differential Revision: https://reviews.llvm.org/D40432 llvm-svn: 320252
* [X86] When inserting into the upper bits of a vXi1 vector, make sure we ↵Craig Topper2017-12-091-1/+2
| | | | | | | | | | shift enough bits if we widened the vector. We may need to widen the vector to make the shifts legal, but if we do that we need to make sure we shift left/right after accounting for the new size. If not we can't guarantee we are shifting in zeros. The test cases affected actually show cases where we should move the shifts all together, but that's another problem. llvm-svn: 320248
* Revert and accidentally committed revert commitDylan McKay2017-12-0912-22/+285
| | | | | | This reverts commit r320245. llvm-svn: 320247
* Revert "[AVR] Override ParseDirective"Dylan McKay2017-12-0912-285/+22
| | | | | | This reverts commit 57c16f9267969ebb09d6448607999b4a9f40c418. llvm-svn: 320245
* [X86] Improve lowering of concats of mask vectors to better optimize zero ↵Craig Topper2017-12-091-59/+44
| | | | | | | | vector inputs. We were previously using kunpck with zero inputs unnecessarily. And we had cases where we would insert into a zero vector and then insert into larger zero vector incurring two sets of shifts. llvm-svn: 320244
* Relax unaligned access assertion when type is byte alignedDylan McKay2017-12-093-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This relaxes an assertion inside SelectionDAGBuilder which is overly restrictive on targets which have no concept of alignment (such as AVR). In these architectures, all types are aligned to 8-bits. After this, LLVM will only assert that accesses are aligned on targets which actually require alignment. This patch follows from a discussion on llvm-dev a few months ago http://llvm.1065342.n5.nabble.com/llvm-dev-Unaligned-atomic-load-store-td112815.html Reviewers: bogner, nemanjai, joerg, efriedma Reviewed By: efriedma Subscribers: efriedma, cactus, llvm-commits Differential Revision: https://reviews.llvm.org/D39946 llvm-svn: 320243
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