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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-12-10 11:51:29 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-12-10 11:51:29 +0000 |
| commit | cd5817111065f8b5b0ced2c526b2dcf586b6269b (patch) | |
| tree | bec7f18fba493cc878e7729e84087da6df6bfd70 /llvm/lib | |
| parent | b7fb2e2fa1666d1a42581931c46af834dd441255 (diff) | |
| download | bcm5719-llvm-cd5817111065f8b5b0ced2c526b2dcf586b6269b.tar.gz bcm5719-llvm-cd5817111065f8b5b0ced2c526b2dcf586b6269b.zip | |
[X86] Flag BTVER2 scheduler model as complete
We just have to locally tag COPY as WriteMove
llvm-svn: 320300
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 685aaf1f140..d7474a28896 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -22,10 +22,6 @@ def BtVer2Model : SchedMachineModel { let HighLatency = 25; let MispredictPenalty = 14; // Minimum branch misdirection penalty let PostRAScheduler = 1; - - // FIXME: SSE4/AVX is unimplemented. This flag is set to allow - // the scheduler to assign a default model to unrecognized opcodes. - let CompleteModel = 0; } let SchedModel = BtVer2Model in { @@ -168,6 +164,9 @@ def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; } def : WriteRes<WriteStore, [JSAGU]>; def : WriteRes<WriteMove, [JALU01]>; +// Treat misc copies as a move. +def : InstRW<[WriteMove], (instrs COPY)>; + //////////////////////////////////////////////////////////////////////////////// // Idioms that clear a register, like xorps %xmm0, %xmm0. // These can often bypass execution ports completely. |
